Bipolar flip-flop circuit with improved noise immunity
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorToshiya Nakano
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Abstract
A semiconductor integrated bipolar flip-flop circuit prevents or suppresses erroneous operation arising from a current induced by external noise and flowing through a parasitic capacitance associated with a p-type diffused resistor. The semiconductor integrated circuit includes bipolar transistors that are directly involved with set and reset operations of the flip-flop circuit having bases connected to a two-stage inverter including bipolar transistors so that the bases of the bipolar transistors involved in setting and resetting are not connected directly to a p-type diffused resistor.
Claims3
A semiconductor integrated flip-flop circuit with bipolar transistors comprising:
- a set/reset circuit section for generating a Q output signal and an inverted-Q output signal, the set/reset circuit section including a plurality of bipolar transistors having respective emitters, bases, and collectors, the transistors performing set and reset operations of the flip-flop circuit;
- and
- erroneous operation suppressing means for suppressing erroneous operation of a first of the transistors due to noise entering the bases of the transistors, wherein the first transistor has its base coupled to a signal output having a fan-out of at least two and is latched in an on-state or an off-state, the erroneous operation suppressing means including a two-stage bipolar transistor inverter circuit and a balance resistor, the two-stage bipolar transistor inverter circuit being coupled between the base of the first transistor and the balance resistor, the balance resistor being coupled to the signal output.
Dependencies are inferred from the claim text.