Hazard-free divider circuit

A digital pulse signal divider circuit for providing an output digital pulse signal having a period one and one-half times that of an input digital pulse signal, said divider circuit comprising:

• a first delay pulse generator, said first pulse generator providing a first output pulse asserted on a first edge of an input distal pulse signal and unasserted on the next edge following said first edge of the input pulse signal;
• a second delay pulse generator, said second pulse generator providing a second output pulse asserted on the third edge following said first edge of the input pulse signal and unasserted on the fourth edge following said first edge of the input pulse signal;
• and
• an output pulse generator for generating an output digital pulse signal, said output pulse generator receiving said first and said second output pulses as inputs, wherein said output pulse generator maintains a selected phase output when either said first or said second output pulses are at the selected phase.