Power saving terminated bus

In an integrated circuit including a first voltage potential, a second voltage potential, and a clock line with a clock signal, a terminator circuit with an input node having a first logic value of either a high logic value or a low logic value during a first clock cycle of the clock signal, comprising:

• a storage device coupled to the clock line and coupled to receive the first logic value of the input node, the storage device sampling the first logic value of the input node at a sampling time determined by the clock signal and supplying the first logic value on a storage device output during a second clock cycle subsequent to the first clock cycle;
• a first termination device selectably coupling the input node to the first voltage potential during the second clock cycle if the storage device output is the high logic value;
• and
• a second termination device selectably coupling the input node to the second voltage potential during the second clock cycle if the storage device output is the low logic value.

In an integrated circuit including a first voltage potential, a second voltage potential, an enable line with an enable signal, a data line with a data signal, and a clock line with a clock signal, a driver/terminator circuit with an interface node having a first input value of either a high logic value or a low logic value during a first clock cycle of the clock signal, comprising:

• a terminate line with a terminate signal;
• a storage device coupled to the clock line and coupled to receive the first input value of the interface node, the storage device sampling the first logic value of the interface node at a sampling time determined by the clock signal and supplying the first logic value on a storage device output during a second clock cycle subsequent to the first clock cycle;
• control logic coupled to the storage device output, the data line, and the terminate line driving a control logic output indicating the storage device output if the terminate signal is active and indicating the data signal if the terminate signal is not active;
• a first driving terminating device coupled to receive the enable signal, the first driving terminating device selectably coupling the first voltage potential to the interface node according to the control logic output if the enable signal is active;
• and
• a second driving terminating device coupled to receive the enable signal, the second driving terminating device selectably coupling the second voltage potential to the interface node according to the control logic output if the enable signal is active.

A terminating circuit including a clock signal on a clock line with a first clock cycle and a second subsequent clock cycle, comprising:

• a bus connection;
• an enable line;
• a comparator having a comparator output line, a positive input coupled to the bus connection, and a negative input coupled to a selected bias line;
• a latch coupled to the comparator output line and coupled to the clock line, the latch containing a first signal level sampled at a time determined by the clock signal from the bus connection during the first clock cycle and indicating the first signal level on a latch output during the second clock cycle;
• a bias multiplexer having a bias multiplexer control coupled to the latch output, a bias multiplexer output coupled to the selected bias line, and a first and a second bias multiplexer input coupled to a first and a second bias voltage line;
• a driving terminating buffer with a buffer input coupled to receive the latch output, a buffer enable coupled to the enable line, and a buffer output coupled to the bus connection.

A computer system including a bus with a signal line, comprising:

• a driving bus agent including:
• a first device identification register which contains a first device identification value;
• a first master identification register which contains a temporary master identification value;
• a first comparison circuit coupled to receive the first device identification value and the temporary master identification value, the first comparison circuit having a first comparison output coupled to a first control bus, the first comparison output indicating that the first device identification value corresponds to the temporary master identification value;
• an output circuit coupled to the control bus, coupled to a first data line, and coupled to the signal line, the output circuit being enabled by the first comparison output and driving the signal line according to a first data value on the data line;
• and
• a terminating bus agent including:
• a second device identification register which contains a second device identification value not equal to the first device identification value, the second identification value having a predetermined relationship to the first identification value;
• a second master identification register which contains the temporary master identification value;
• a second comparison circuit coupled to receive the second device identification value and the temporary master identification value, the second comparison circuit having a second comparison output coupled to a second control bus, the second comparison output indicating that the second device identification value has the predetermined relationship to the temporary master identification value;
• and
• a termination circuit coupled to the control bus and the signal line, the termination circuit enabled to terminate the signal line by the second comparison output.

A method of sending and receiving data represented using a high and a low value in a computer system with a clock signal having a first clock cycle and a second clock cycle subsequent to the first clock cycle, comprising the steps of:

• driving a first data value on a signal line during the first clock cycle;
• terminating the signal line to an initial voltage potential representing of either of the high and the low value during the first clock cycle;
• sampling at a sampling time a first sampled value equal to the first data value, the sampling time determined by the clock signal;
• driving a second data value on the signal line during the second clock;
• terminating the signal line to a first voltage potential during the second clock cycle if the first sampled value is the high value;
• and
• terminating the signal line to a second voltage potential during the second clock cycle if the first sampled value is the low value.

A method of driving and terminating a signal line in a computer system having a plurality of bus agents including a first agent with a first agent identification value and a second agent with a second agent identification value, comprising the steps of:

• a) determining a temporary bus master identification value for one of the plurality of bus agents which will next drive the bus;
• b) if the temporary bus master identification value indicates the first agent identification value then
• b.1) driving the signal line with the first bus agent;
• b.2) terminating the signal line with only the second bus agent;
• and
• c) if the temporary bus master identification value indicates the second agent identification value then
• c.1) driving the signal line with the second bus agent;
• c.2) terminating the signal line with only the first bus agent.