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US 5,517,443 AGranted
Method and system for protecting a stacked gate edge in a semi-conductor device from self aligned source (SAS) etch in a semi-conductor device
AssigneeAdvanced Micro Devices, Inc.
InventorsDavid K. Y. Liu, Yu Sun, Chi Chang
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Abstract
A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.
Claims6
A system for protecting a stacked gate edge to minimize damage to a tunnel oxide region and to maintain source junction uniformity of a semiconductor device comprising:
- means for providing the stacked gate edge on the semiconductor device;
- means for performing a source implant on the semiconductor device;
- means responsive to the stacked gate edge providing means for providing a spacer on the stacked gate edge;
- and
- means responsive to the spacer providing means for providing a self aligned source (SAS) etch on the semiconductor device.
2 more elements
Dependencies are inferred from the claim text.