Semiconductor integrated circuit device having component transistor with protected gate electrode
AssigneeNEC Corporation
InventorKunihiro Koyabu
Life of this patent
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Abstract
An inverter incorporated in a semiconductor integrated circuit device is implemented by a series combination of a p-channel enhancement type field effect transistor and an n-channel enhancement type field effect transistor coupled between a positive power voltage line and a ground voltage line, the p-channel enhancement type field effect transistor and the n-channel enhancement type field effect transistor have a common gate electrode coupled through normally-off protective transistors to the positive power voltage line and the ground voltage line, and excess electric charges are discharged through a parasitic diode between the drain region and a substrate of either protective transistor so as to prevent gate oxide films from the excess electric changes.
Claims11
A semiconductor integrated circuit device fabricated on a semiconductor substrate having a first field effect transistor, said semiconductor integrated circuit device comprising:
- source and drain regions formed in a surface portion of said semiconductor substrate,
- a gate electrode layer covering said surface portion,
- said gate electrode extending on a gate insulating layer of said field effect transistor, a voltage level of said gate electrode being controlled such that said voltage is not permitted to change outside of a predetermined range in a standard operation of said semiconductor integrated circuit device;
- an inter-level insulating film structure having a first inter-level insulating layer covering said semiconductor substrate and a second inter-level insulating layer covering said first inter-level insulating layer;
- a multi-level wiring structure having a plurality of power supply lines and signal lines, said multi-level wiring structure comprising:
- a plurality of first-level wirings extending on said first inter-level insulating layer, with a first contact hole being formed in said first inter-level insulating layer, such that said first level wirings connect said first inter-level insulating layer to said gate electrode through said first contact hole, and
- a plurality of second-level wirings extending on said second inter-level insulating layer, with a second contact hole being formed in said second inter-level insulating layer, such that said second level wirings selectively connect said second inter-level insulating layer to said first-level wirings and to said field effect transistor through said first contact hole;
- a first parasitic diode coupled between said gate electrode and one of said power supply lines, said parasitic diode having a threshold, said threshold determining said predetermined range such that electric charges are allowed to flow through said diode to a constant voltage source when said gate electrode exceeds said threshold, said exceeding of said threshold typically occurring in a manufacturing process of said semiconductor integrated circuit device.
Dependencies are inferred from the claim text.