Method of making high coupling ratio NAND type flash memory

The method of forming a memory cell with improved coupling ratio comprising:

• providing a layer of silicon dioxide over the surface of a semiconductor substrate;
• depositing a layer of silicon nitride over said silicon dioxide layer and patterning said silicon nitride layer;
• forming silicon nitride spacers on the sidewalls of said patterned silicon nitride layer whereby a portion of said silicon dioxide layer is covered with silicon nitride;
• removing said silicon dioxide layer not covered by said patterned silicon nitride layer and said silicon nitride spacers wherein portions of said semiconductor substrate are exposed;
• removing said silicon nitride spacers and said silicon nitride layer;
• thereafter growing a tunnel oxide layer on said exposed portions of said semiconductor substrate to a thickness of between about 60 to 100 Angstroms;
• depositing a first polysilicon layer over the surface of said silicon dioxide and said tunnel oxide layers and patterning said first polysilicon layer to form a floating gate;
• depositing a dielectric layer over said patterned first polysilicon layer;
• depositing a conducting layer overlying said dielectric layer and patterning said conducting layer to form a control gate;
• and
• providing passivation and metallization to complete the fabrication of said memory cell with improved coupling ratio.

The method of forming a memory cell with improved coupling ratio comprising:

• providing a layer of silicon dioxide over the surface of a semiconductor substrate;
• depositing a layer of silicon nitride over said silicon dioxide layer and patterning said silicon nitride layer;
• forming silicon nitride spacers on the sidewalls of said patterned silicon nitride layer whereby a portion of said silicon dioxide layer is covered with silicon nitride;
• removing said silicon dioxide layer not covered by said patterned silicon nitride layer and said silicon nitride spacers wherein portions of said semiconductor substrate are exposed and wherein said exposed portions of said semiconductor substrate have a shape wherein there are four approximately equal sides;
• thereafter growing a tunnel oxide layer on said exposed portions of said semiconductor substrate;
• removing said silicon nitride spacers and said silicon nitride layer;
• depositing a first polysilicon layer over the surface of said silicon dioxide and said tunnel oxide layers and patterning said first polysilicon layer to form a floating gate;
• depositing a dielectric layer over said patterned first polysilicon layer;
• depositing a conducting layer overlying said dielectric layer and patterning said conducting layer to form a control gate;
• and
• providing passivation and metallization to complete the fabrication of said memory cell with improved coupling ratio.