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US 5,515,313 AGranted
Static-type semiconductor memory device
AssigneeNEC Corporation
InventorTakashi Yamaguchi
Life of this patent
Estimating the term…
Abstract
A static-type memory cell includes a flip-flop circuit formed with a pair of N-channel type MOS transistors for driving provided in a semiconductor substrate and a pair of P-channel type MOS transistor as load elements provided in the upper layer of the pair of driving N-channel type MOS transistors and formed with thin film transistors. The gate electrodes of the pair of P-channel type MOS transistor are load elements and are formed of polycrystalline silicon layers containing 2 to 45 atoms % of oxygen for maintaining high resistance in the P-channel type MOS transistor and thereby provide satisfactory resistance against soft errors.
Claims17
A static-type memory cell comprising:
- a flip-flop formed with a pair of driving N-channel type MOS transistors provided in a semiconductor substrate, and a pair of P-channel type MOS transistors, formed with thin film transistors, constituting load elements provided in the upper layer of said pair of driving N-channel type MOS transistors;
- gate electrodes of said pair of P-channel type MOS transistors constituting load elements, and being formed of polycrystalline silicon layers containing 2 to 45 atoms % of oxygen.
A static-type semiconductor memory device comprising:
- a memory cell array constituted of flip-flops, each being formed with a pair of driving N-channel type MOS transistors provided in a semiconductor substrate, and a pair of P-channel type MOS transistors, formed with thin film transistors, constituting load elements provided in the upper layer of said pair of driving N-channel type MOS transistors;
- gate electrodes of said pair of P-channel type MOS transistors constituting load elements, and being formed of polycrystalline silicon layers containing 2 to 45 atoms % of oxygen.
A static-type memory cell comprising:
- a flip-flop formed with a pair of driving N-channel type MOS transistors provided in a semiconductor substrate, and a pair of P-channel type MOS transistors, formed with thin film transistors, constituting load elements provided in the upper layer of said pair of driving N-channel type MOS transistors, said P-channel type MOS transistors including gate electrodes formed of polycrystalline silicon layers containing 2 to 45 atoms % of oxygen.
A static-type semiconductor memory device comprising:
- a memory cell array constituted of flip-flops, each flip-flop being formed with a pair of driving N-channel type MOS transistors provided in a semiconductor substrate, and a pair of P-channel type MOS transistors, formed with thin film transistors, constituting load elements provided in the upper layer of said pair of driving N-channel type MOS transistors, said P-channel type MOS transistors including gate electrodes formed of polycrystalline silicon layers containing 2 to 45 atoms % of oxygen.
A static-type semiconductor memory device comprising:
- a flip-flop formed with a pair of driving N-channel type MOS transistors provided in a semiconductor substrate, and a pair of P-channel type MOS transistors, formed with thin film transistors, as load elements provided in the upper layer of said pair of driving N-channel type MOS transistors;
- a pair of N-channel type MOS transistors as transfer gates respectively provided between complementary data storage nodes of said flip-flop and complementary bit lines;
- wherein gate electrodes of said pair of P-channel type MOS transistors constituting load elements being formed of polycrystalline silicon layers containing 2 to 45 atoms % of oxygen.
A static-type semiconductor memory device comprising:
- a memory cell array constituted by flip-flops, each being formed with a pair of driving N-channel type MOS transistors provided in a semiconductor substrate, and a pair of P-channel type MOS transistors, formed with thin film transistors, as load elements provided in the upper layer of said pair of driving N-channel type MOS transistors, and a pair of N-channel type MOS transistors as transfer gates respectively provided between complementary data storage nodes of said flip-flops and complementary bit lines;
- wherein gate electrodes of said pair of P-channel type MOS transistors constituting load elements being formed of polycrystalline silicon layers containing 2 to 45 atoms % of oxygen.
A static-type semiconductor memory device comprising:
- a flip-flop formed with a pair of driving N-channel type MOS transistors provided in a semiconductor substrate, and a pair of P-channel type MOS transistors, formed with thin film transistors, as load elements provided in the upper layer of said pair of driving N-channel type MOS transistors;
- a pair of N-channel type MOS transistors as transfer gates respectively provided between complementary data storage nodes of said flip-flop and complementary bit lines;
- said P-channel type MOS transistors including gate electrodes formed of polycrystalline silicon layers containing 2 to 45 atoms % of oxygen.
A static-type semiconductor memory device comprising:
- a memory cell array constituted by flip-flops, each being formed with a pair of driving N-channel type MOS transistors provided in a semiconductor substrate and a pair of P-channel type MOS transistors, as formed with thin film transistors, as load elements provided in the upper layer of said pair of driving N-channel type MOS transistors, and a pair of N-channel type MOS transistors as transfer gates respectively provided between complementary data storage nodes of said flip-flop and complementary bit lines;
- said P-channel type MOS transistors including gate electrodes formed of polycrystalline silicon layers containing 2 to 45 atoms % of oxygen.
Dependencies are inferred from the claim text.