Mutlilayered antifuse with intermediate metal layer
AssigneeCrosspoint Solutions, Inc.
InventorAli A. Iranmanesh
Life of this patent
Estimating the term…
Abstract
An antifuse structure in an integrated circuit including a first interconnection line, a second interconnection line formed over the first interconnection line, and a plurality of programming layers between the first and second interconnection lines. Each pair of programming layers has a metal layer therebetween which dissolves with the programming layers to form a conducting link during the programming of such antifuse structure. Such antifuse structure may also include a conductive plug between the programming layers and the second interconnection line.
Claims16
An antifuse structure in an integrated circuit comprising:
- a first interconnection line;
- a second interconnection line formed over said first interconnection line;
- a first substantially nonconducting programming layer between said first interconnection line and said second interconnection line;
- a second substantially nonconducting programming layer between said first interconnection line and said second interconnection line;
- and
- a metal layer disposed between said first programming layer and said second programming layer;
- whereby during the programming of said antifuse structure, said metal layer combines with said first programming layer and said second programming layer to form a conducting link between said first interconnection line and said second interconnection line.
An antifuse structure in an integrated circuit formed on a substrate comprising:
- an insulating layer disposed on the substrate;
- a first interconnection line disposed on said insulating layer;
- a second interconnection line formed over said first interconnection line;
- a second insulating layer having a top insulating surface, said second insulating layer being interposed between said first and second interconnection lines;
- a via disposed in said second insulating layer;
- a conducting plug disposed in said via, said plug contacting said first interconnection line and having a top plug surface substantially equiplanar with said top insulating surface;
- a layer of barrier metal disposed on said top plug surface and at least a portion of said top insulating surface, said barrier metal having a predetermined viscosity so as to smooth irregularities on said top plug surface;
- and
- a programming layer located between said layer of barrier metal and said second interconnection line.
An antifuse structure in an integrated circuit comprising:
- a first interconnection line;
- a second interconnection line formed over said first interconnection line;
- an insulating layer between said first and second interconnection lines;
- a via disposed in said insulating layer, said via having side walls;
- a conducting plug substantially filling the via, said conducting plug contacting said side walls;
- a layer of barrier metal on top of said plug;
- and
- a programming layer located between said layer of barrier metal and said second interconnection line.
Dependencies are inferred from the claim text.