Protection circuit device for a semiconductor integrated circuit device

A semiconductor device comprising:

• first and second signal pins;
• first and second power supply pins;
• a first internal circuit coupled to said first signal pin and operating on a power voltage of said first power supply pin;
• a first protective circuit coupled between said first signal pin and said first power supply pin, which, when rendered operative, discharges first charges at said first signal pin to said first power supply pin to protect said first internal circuit;
• a second internal circuit coupled to said second signal pin and operating on a power voltage of said second power supply pin;
• a second protective circuit coupled between said second signal pin and said second power supply pin, which, when rendered operative, discharges second charges at said second signal pin to said second power supply pin to protect said second internal circuit;
• and
• switching means coupled between said first and second power supply pins, wherein, should disconnection of said power supply voltage occur at one of said first and second power supply pins, said switching means is rendered conductive, said switching means thus preventing an associated one of said first and second protective circuits from discharging an associated one of said first and second charges, said switching means thereby allowing said associated one of said first and second protective circuits to discharge said associated one of said first and second charges to the other of said first and second power supply pins through said switching means, said switching means comprising:
• a semiconductor substrate of a first conductivity type;
• first and second diffusion layers of a second conductivity type formed separately from and near to each other in a surface region of said semiconductor substrate;
• an insulation film formed on surfaces of said first and second diffusion layers and said semiconductor substrate;
• first and second electrodes formed on said first and second diffusion layers respectively, said first and second electrodes being respectively connected to said first and second protection circuits;
• and
• first and second gate electrodes formed on said insulation film over a channel region in said semiconductor substrate between said first and second diffusion regions, said first and second gate electrodes being respectively connected to said first and second electrodes, said first and second gate electrodes being spaced apart from each other.