Non-volatile semiconductor memory device and method for manufacturing the same

An EEPROM semiconductor memory device comprising:

• a semiconductor substrate having a first conductivity type, said semiconductor substrate being divided into a cell array region and a peripheral circuit region;
• a first impurity-doped region having said first conductivity type formed in a first surface portion of said semiconductor substrate in said cell array region;
• a second impurity-doped region having a second conductivity type formed in said first surface portion of said semiconductor substrate in said cell array region, said second impurity-doped region enclosing said first impurity-doped region;
• a memory cell comprising:
• a memory source region and a memory drain region formed on a surface portion of said first impurity-doped region, and
• a floating electrode formed on said first impurity-doped region and a control electrode formed on said floating electrode;
• a third impurity-doped region having said first conductivity type formed in a first surface portion in said peripheral circuit region of said semiconductor substrate;
• a first MOS transistor comprising:
• first source and drain regions formed in respective surface portions of said third impurity-doped region, and
• a first gate electrode formed on said third impurity-doped region;
• a second MOS transistor comprising:
• second source and drain regions formed directly in respective second surface portions in said peripheral circuit region of said semiconductor substrate, and
• a second gate electrode formed on said semiconductor substrate;
• a fourth impurity-doped region having said second conductivity type and being formed in a third surface portion in said peripheral circuit region of said semiconductor substrate;
• and
• a third MOS transistor comprising:
• third source and drain regions formed in respective surface portions of said fourth impurity-doped region, and
• a third gate electrode formed on said fourth impurity-doped region.