US 5,514,882 A · Bistable four layer device memory cell and method for storing and retrieving binary information

Abstract

A new static memory cell based on the bistable operation of a three-terminal four layer semiconductor device working in the forward blocking state is disclosed. The power consumption of the memory cell is low. The switching speed of the memory cell is in the nanosecond range. The memory cell may be integrated into VLSI processes and is of a size suitable for VLSI applications. The memory cell comprises a semiconductor device which comprises: an n-type semiconductor cathode region; a p-type semiconductor gate region; a third semiconductor region adjacent the gate region; a fourth region adjacent the third semiconductor region; and a hole-injecting boundary between the third semiconductor region and the fourth region. The semiconductor device is preferably a p-n-p-n device. The gate current-voltage characteristics of the device comprise a negative resistance region. The device is designed to operate in a forward blocking low current state. The memory cell further comprises a gate load element and a power supply for biasing the device. When the device is properly biased and is connected to a suitable gate load element it can operate in one of two bistable states characterized by different gate-cathode voltages. The state of the device can be switched by applying suitable pulses to the gate.

Claims14

Dependent claims

A method for storing binary information, said method comprising the steps of:

(a) providing:
i. a data line for carrying said binary information;
ii. a semiconductor device comprising an anode, a cathode and a gate, wherein, while an anode-cathode bias voltage is maintained within a voltage range, said semiconductor device is in an "off" state characterized by high impedance between said anode and cathode, has a current gain greater than 1, has a gate current-voltage curve comprising a negative resistance region and has a pair of bistable states characterized by gate voltages V.sub.G1 and V.sub.G2 ;
iii. a field effect transistor having a gate, a source and a drain connected between said data line and said gate by said source and drain;
iv. a read/write control line operatively connected to said gate of said field effect transistor;
and
v. biasing means for applying a bias voltage to said anode with respect to said cathode;
(b) applying said bias voltage within said voltage range to said device;
(c) writing a bit of information to said device by the steps of:
i. setting said data line to a voltage either higher than V.sub.G2 or lower than V.sub.G1 ;
ii. applying a voltage to said read/write control line to switch said field effect transistor into a low impedance state;
and
iii. changing said voltage on said read/write control line to switch said field effect transistor into a high impedance state.

10 more elements

Dependencies are inferred from the claim text.

Bistable four layer device memory cell and method for storing and retrieving binary information

Life of this patent

Bistable four layer device memory cell and method for storing and retrieving binary information

Life of this patent

Abstract

Claims14