Method of producing a semiconductor memory device having thin film transistor load

A method of producing a memory cell on a semiconductor substrate, the memory cell including two transfer transistors, two driver transistors, two thin film transistor loads, and two memory capacitors, said method comprising:

• forming a field insulator layer on the semiconductor substrate;
• forming a gate insulator layer above the field insulator layer;
• forming a gate electrode of a respective driver transistor by forming and patterning a first conductor layer above the gate insulator layer;
• forming impurity regions in the semiconductor substrate using the field insulator layer and the first conductor layer as masks;
• forming a first insulator layer after forming the impurity regions;
• forming source, drain and channel regions of a respective thin film transistor load by forming a second conductor layer and selectively injecting impurities into the second conductor layer;
• patterning the second conductor layer.;
• forming an upper gate insulator layer of the respective thin film transistor load above the second conductor layer by forming a second insulator layer after patterning the second conductor layer;
• forming a third conductor layer above the upper gate insulator layer;
• forming a third insulator layer above the third conductor layer;
• forming a contact hole which extends from the third insulator layer, through the third conductor layer and the second conductor layer, and reaches the first conductor layer;
• (h) forming a storage electrode of the memory capacitor by forming a fourth conductor layer which makes contact with the first conductor layer, the second conductor layer and the third conductor layer through the contact hole;
• patterning the fourth conductor layer, the third insulator layer and the third conductor layer, the patterned fourth conductor layer forming a fin of the memory capacitor and an upper gate electrode of a respective thin film transistor load, the patterned third insulator layer forming a spacer of the memory capacitor between the storage electrode of the memory capacitor and the upper gate electrode;
• removing the third insulator layer;
• and
• successively forming a dielectric layer covering the storage electrode of the memory capacitor and a fifth conductor layer forming an opposing electrode of the memory capacitor, said opposing electrode also functioning as a ground line.

A method of producing a a memory cell on a semiconductor substrate, the memory cell including two transfer transistors, two driver transistors, two thin film transistor loads, and two memory capacitors, said method comprising:

• forming a field insulator layer on the semiconductor substrate;
• forming a gate insulator layer above the field insulator layer;
• forming a gate electrode of a respective driver transistor by forming and patterning a first conductor layer above the gate insulator layer;
• forming impurity regions in the semiconductor substrate using the field insulator layer and the first conductor layer as masks;
• forming a first insulator layer after forming the impurity regions;
• forming a lower gate electrode of a respective thin film transistor load by forming and patterning a second conductor layer above the first insulator layer;
• forming a lower gate insulator layer of the respective thin film transistor load by forming a second insulator layer above the second conductor layer;
• forming source, drain and channel regions of the respective thin film transistor load by forming a third conductor layer above the lower gate insulator layer and selectively injecting impurities into the third conductor layer;
• patterning the third conductor layer;
• forming a third insulator layer above the third conductor layer;
• forming a fourth conductor layer above the third insulator layer;
• forming a fourth insulator layer above the fourth conductor layer;
• forming a contact hole which extends from the fourth insulator layer, through the third conductor layer and the second conductor layer and reaches the first conductor layer;
• forming a storage electrode of the memory capacitor by forming a fifth conductor layer which makes contact with the first conductor layer, the second conductor layer, the third layer and the fourth conductor layer through the contact hole;
• patterning the fifth conductor layer, the fourth insulator layer and the fourth conductor layer, the patterned fifth and fourth conductor layers forming fins of the memory capacitor, the patterned fourth insulator layer forming a spacer of the memory capacitor between the storage electrode of the memory capacitor and the upper gate electrode of the respective thin film transistor load;
• removing the fourth insulator layer;
• and
• successively forming a dielectric layer covering the storage electrode of the memory capacitor and a sixth conductor layer forming an opposing electrode of the memory capacitor, said opposing electrode also functioning as a shield electrode of the thin film transistor load.