Through glass ROM code implant to reduce product delivering time

A method of manufacturing an integrated circuit device comprising the steps of:

• providing a partially completed semiconductor device comprising a gate electrode, a channel region, a source region, and a drain region;
• forming a dielectric layer overlying said gate electrode, said source region, and said drain region;
• exposing said source region and said drain region;
• forming contact plugs on said exposed source region and said exposed drain region;
• forming a recessed region on a portion of said dielectric layer overlying said gate layer;
• and
• implanting impurities through said recessed region and said gate electrode.

A method of implanting impurities in an integrated circuit device comprising the steps of:

• providing a partially completed semiconductor device comprising a polysilicon layer overlying a substrate;
• forming a dielectric layer overlying said polysilicon layer;
• forming a recessed region on a portion of said dielectric layer overlying said polysilicon layer;
• implanting impurities comprising an absolute charge greater than one electron volt through said recessed region and said polysilicon layer;
• and
• annealing said implant to drive-in said impurities into said substrate.

A method of making a read only memory comprising the steps of:

• forming MOS transistors in a ROM region of an integrated circuit, said MOS transistors comprising a dielectric layer thereon, said dielectric layer comprising a BPSG layer overlying an oxide layer;
• storing said integrated circuit;
• and
• programming said ROM region by the steps of etching a thickness of said dielectric layer from gate regions of selected MOS transistors and implanting impurities through said gate regions into channel regions of said selected MOS transistors, wherein said BPSG layer and oxide layer have a combined thickness ranging from about 1,500 .ANG. to about 2,500 .ANG..