US 5,513,064 A · Method and device for improving I/O ESD tolerance

Abstract

An input protection device is presented for improving I/O electrostatic discharge ESD tolerance. The present invention protects a selected device by providing a sufficient potential difference between the substrate and the source of the device in question to protect it against an electrostatic discharge. In one embodiment of the invention, a resistor is placed between the substrate and the internal V.sub.SS connection. All V.sub.SS to substrate contacts have to be removed for internal V.sub.SS busses to be maintained at a predetermined resistance between the substrate and V.sub.SS. In other embodiments of the invention, an active device is placed between the substrate and the internal V.sub.SS connection. As with the first described embodiment, all V.sub.SS to substrate contacts have to be removed for internal V.sub.SS busses to be maintained at a predetermined resistance between the substrate and V.sub.SS. The active device presents a high impedance when not powered on and is very conductive when powered on.

Claims3

Dependent claims

A semiconductor protection circuit comprising:

a lightly doped region of a first conductivity type at a face of a substrate;
a field effect transistor, formed in said lightly doped region and having heavily doped source and drain terminals of a second conductivity type;
a bond pad coupled to one of said source and drain terminals;
an internal reference bus coupled to another of said source and drain terminals;
an external reference bus coupled to said substrate;
and
a resistive device for coupling said internal reference bus to said external reference bus.

4 more elements

Dependencies are inferred from the claim text.

Method and device for improving I/O ESD tolerance

Life of this patent

Method and device for improving I/O ESD tolerance

Life of this patent

Abstract

Claims3