Semiconductor chip packages

A package for one or more integrated circuits contained therein, the package being adapted for stacking with identical ones of such packages, comprising:

• a package for containing one or more integrated circuit chips;
• integrated circuitry comprising one or more integrated circuits located within the package;
• the package having first, second, third and fourth sides;
• an imaginary first axis of symmetry located between the first and third sides;
• first, second and third groups of pins located symmetrically on said package, said third group consisting of at least one pin;
• said first group of pins being electrically coupled to said integrated circuitry in the package, said first group of pins being located on said first and third sides of the package;
• said second group of pins not being electrically coupled to the integrated circuitry in the package, said second group of pins being located on said first side of the package;
• said third group of pins being electrically coupled to the integrated circuitry in the package, said third group of pins being located on said third side of the package and disposed at a location that is reflectively symmetric to said second pins, with respect to said imaginary axis, so that said third pins are located opposite to said second pins;
• said first group of pins being organized into and comprising two or more sets of pins, each respective set of said first group of pins having two or more pins;
• said integrated circuit being coupled to receive at least two types of signals;
• each said set in said first group of pins being identified with and coupled to conduct a corresponding one of said types of signals to be received by said integrated circuitry;
• within said first group of pins, any two or more power supply pins forming a first set, any two or more data pins forming a second set, any two or more address pins forming a third set;
• and any two or more ground pins forming a fourth set;
• each set of said first group of pins comprising pins that are located on both said first and third sides of said package at locations that are reflectively symmetric about said imaginary axis, whereby the pins of the first set are located on the first and third sides of the package at locations that are reflectively symmetric to each other with respect to the imaginary axis, and the pins of the second set are located on the first and third sides of the package at locations that are reflectively symmetric to each other with respect to the imaginary axis;
• the first group of pins being positioned so that when a said integrated circuit package is stacked with another like integrated circuit package, the first group of pins of one said package is aligned over said first group of pins of the other package;
• the third group of pins being positioned so that when said integrated circuit package is so stacked, at least one pin of the third group of pins of one package is aligned with at least one pin of the second group of pins of the other package;
• whereby the relative configuration of the first, second and third groups of pins allows identical integrated circuit packages to be stacked and functionally interconnected.

A semiconductor chip package comprising:

• a chip package;
• at least one semiconductor chip disposed in said package;
• a plurality of pins disposed on the package, the pins comprising pairs of matching first pins connected to circuitry in the package for conducting first types of signals, the pins of each pair being arranged to conduct respective signals having a similar function;
• at least one second pin disposed on and connected to circuitry in the package for conducting signals of a second type, the semiconductor chip package being responsive to one or more of said signals of a second type;
• and
• at least one third pin disposed on the package, the at least one third pin being a redundant pin which is not connected to circuitry in the package;
• the distribution of the first, second and third pins being such that first and second packages may be located adjacent each other with each first pin on the first package connecting with a matching first pin on the second package and with said at least one second pin on the first package connecting with said at least one third pin on the second package.

A package for one or more integrated circuits contained therein, the package being adapted for stacking with identical ones of such packages, comprising:

• a chip package;
• an integrated circuit located within the package;
• the package having first, second, third and fourth sides;
• an imaginary first axis of symmetry located between the first and third sides;
• a plurality of pins located symmetrically on said package, including first pins connected to the integrated circuit within the package for receiving and supplying address signals, data signals, power supply signals, and a ground signal;
• the pins for supplying the address signals being symmetrically located about said axis;
• the pins for supplying the data signals being symmetrically located about said axis;
• the pins for supplying the power supply signals being symmetrically located about said axis;
• the pins for supplying the ground signals being symmetrically located about said axis;
• said plurality of pins including one or more unconnected pins which are not electrically coupled to the integrated circuit in the package, said unconnected pins being located on said first side of the package;
• said plurality of pins including one or more chip enable pins electrically coupled to the integrated circuit in the package, said chip enable pins being located on said third side of the package and disposed at a location that is reflectively symmetric to said unconnected pins, with respect to said imaginary axis, so that said chip enable pins are located opposite to said unconnected pins;
• the first pins being positioned so that when a said integrated circuit package is stacked with another like integrated circuit package, the first pins of one said package are aligned over said first pins of the other package;
• the chip enable pins being positioned so that when said packages are stacked, at least one of the chip enable pins of one package is aligned with at least one unconnected pin of the other package;
• whereby the relative configuration of the pins allows identical integrated circuit packages to be stacked and functionally interconnected.