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US 5,512,772 AGranted
Semiconductor device having bipolar transistor and MOS transistor
AssigneeKabushiki Kaisha Toshiba
InventorsTakeo Maeda, Hiroshi Momose, Yukihiro Urakawa, Masataka Matsui
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Abstract
A semiconductor device of this invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is hetero-bipolar transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.
Claims9
A BiCMOS device comprising:
- an emitter coupled logic (ECL) logic circuit including a plurality of bipolar transistors, said ECL logic circuit comprising:
- a first bipolar transistor including a base to which a predetermined voltage is applied, an emitter which is connected to a second power terminal with a first resistance interposed therebetween, and a collector from which a first output voltage is output;
- a second bipolar transistor including a base to which a predetermined voltage is applied, and an emitter which is connected to said second power terminal with a second resistance interposed therebetween;
- a third bipolar transistor including a base to which a predetermined voltage is applied, an emitter which is connected to said second power terminal with a third resistance interposed therebetween, and a collector from which a second output voltage is output;
- a fourth bipolar transistor including an emitter which is connected to the collector of said first bipolar transistor, and a collector which is connected to said first power terminal;
- a fifth bipolar transistor including an emitter which is connected to the collector of said third bipolar transistor, and a collector which is connected to said first power terminal;
- a sixth bipolar transistor including a base to which an input voltage is applied, an emitter which is connected to the collector of said second bipolar transistor, and a collector which is connected to said first power terminal with the fourth transistor interposed therebetween, and which is connected to the base of said fourth bipolar transistor;
- and
- a seventh bipolar transistor including a base to which a reference voltage is applied, an emitter which is connected to the collector of said second bipolar transistor, and a collector which is connected to said first power terminal with the fifth transistor interposed therebetween, and which is connected to the base of said fifth bipolar transistor, and
- wherein each of said bipolar transistors is a hetero-bipolar transistor comprising:
- a semiconductor substrate of a first conductivity type,
- a semiconductor region of a second conductivity type formed in said semiconductor substrate,
- a field oxide film formed on said semiconductor region,
- a first semiconductor layer of the first conductivity type formed in contact with said semiconductor region and formed to lie over said field oxide film, and
- a second semiconductor layer of the second conductivity type formed on said first semiconductor layer,
- said second semiconductor layer having a low density impurity region which is in contact with said first semiconductor layer and a high density impurity region which is formed on said low density impurity region.
13 more elements
A semiconductor device comprising:
- a semiconductor chip;
- a plurality of MOS transistors formed on said semiconductor chip;
- and
- a plurality of bipolar transistors formed on said semiconductor chip,
- wherein at least one of said plurality of bipolar transistors comprises:
- a semiconductor substrate of a first conductivity type;
- a first semiconductor region of a first conductivity type which is formed in said semiconductor substrate;
- a first source region and first drain region of a second conductivity type which are formed in said first semiconductor region;
- and
- a gate electrode which is formed between said first source region and said first drain region;
- at least one remaining bipolar transistor of said plurality of bipolar transistors, comprising:
- a semiconductor substrate;
- a second semiconductor region of a second conductivity type which is formed in said semiconductor substrate;
- a second source region and second drain region of a first conductivity type which are formed in said second semiconductor region;
- and
- a gate electrode which is formed on said semiconductor substrate between said second region and said drain region, and
- wherein each of said bipolar transistors is formed of a hetero-bipolar transistor having a heterojunction, and wherein each of said hetero-bipolar transistors comprises:
- a semiconductor substrate of said first conductivity type;
- a third semiconductor region of said second conductivity type formed in said semiconductor substrate;
- a field oxide film formed on said semiconductor region;
- a first semiconductor layer of the first conductivity type formed in contact with said semiconductor region and formed to lie over said field oxide film, and
- a second semiconductor layer of the second conductivity type formed on said first semiconductor layer,
- said second semiconductor layer having a low density impurity region which is in contact with said first semiconductor layer and a high density impurity region which is formed on said low density impurity region.
20 more elements
A BiCMOS device comprising:
- a first P-type MOS transistor having a gate connected to an input terminal, having a source connected to a first power terminal, and having a drain;
- a first N-type MOS transistor having a gate connected to said input terminal, having a source connected to a second power terminal, and having a drain;
- a second N-type MOS transistor having a gate connected to said input terminal, having a drain connected to an output terminal, and having a source;
- a third N-type MOS transistor having a gate connected to the drains of said first P-type MOS transistor and said first N-type MOS transistor, having a source connected to said second power terminal, and having a drain connected to the source of said second N-type MOS transistor;
- a first NPN-type bipolar transistor, including a collector connected to said first power terminal, a base connected to the drains of said first P-type MOS transistor and said first N-type MOS transistor, and an emitter connected to said output terminal;
- and
- a second NPN-type bipolar transistor, including a collector connected to said output terminal, a base connected to the source of said second N-type MOS transistor and the drain of said third N-type MOS transistor, and an emitter connected to said second power terminal, wherein at least one of said first NPN-type bipolar transistor and said second NPN-type bipolar transistor comprises a hetero-bipolar transistor having a heterojunction,
- said device operable when a voltage V.sub.CC is applied to said first power terminal, said voltage V.sub.CC expressed by the following equation:
- VCC (hetero)=VCC (homo)-2.increment.V.sub.f
- where the V.sub.CC (homo) is a high level power source voltage of a BiCMOS device comprising a homo-bipolar transistor, and .increment.V.sub.f is a value obtained by subtracting a voltage applied between a base and emitter of said homo-bipolar transistor from a voltage applied between a base and emitter of a hetero-bipolar transistor.
7 more elements
A BiCMOS device comprising:
- an emitter coupled logic (ECL) logic circuit including a plurality of bipolar transistors, said ECL logic circuit comprising:
- a first bipolar transistor including a base to which a predetermined voltage is applied, an emitter which is connected to a second power terminal with a first resistance interposed therebetween, and a collector from which a first output voltage is output;
- a second bipolar transistor including a base to which a predetermined voltage is applied, and an emitter which is connected to said second power terminal with a second resistance interposed therebetween;
- a third bipolar transistor including a base to which a predetermined voltage is applied, an emitter which is connected to said second power terminal with a third resistance interposed therebetween, and a collector from which a second output voltage is output;
- a fourth bipolar transistor including an emitter which is connected to the collector of said first bipolar transistor, and a collector which is connected to said first power terminal;
- a fifth bipolar transistor including an emitter which is connected to the collector of said third bipolar transistor, and a collector which is connected to said first power terminal;
- a sixth bipolar transistor including a base to which an input voltage is applied, an emitter which is connected to the collector of said second bipolar transistor, and a collector which is connected to said first power terminal with the fourth transistor interposed therebetween, and which is connected to the base of said fourth bipolar transistor;
- and
- a seventh bipolar transistor including a base to which a reference voltage is applied, an emitter which is connected to the collector of said second bipolar transistor, and a collector which is connected to said first power terminal with the fifth transistor interposed therebetween, and which is connected to the base of said fifth bipolar transistor, and
- wherein each of said bipolar transistors is a hetero-bipolar transistor and said device is operable upon application of a high level power source voltage VCC (hetero) of said ECL logic circuit expressed by the following equation:
- VCC (hetero)=VCC (homo)-2.increment.V.sub.f
- where the VCC (homo) is a high level power source voltage of a BiCMOS device comprising a homo-bipolar transistor, and .increment.V.sub.f is a value obtained by subtracting a voltage applied between a base and emitter of said homo-bipolar transistor from a voltage applied between a base and emitter of a hetero-bipolar transistor.
9 more elements
Dependencies are inferred from the claim text.