US 5,512,765 AGranted

Extendable circuit architecture

AssigneeNational Semiconductor Corporation

InventorTimothy L. Gaverick

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Abstract

A high functional capacity semiconductor based system for which the semiconductor material cost increases substantially linearly with functional capacity. The device is manufactured by taking individual, lower functional capacity devices having an extendible architecture and utilizing them in a high interconnect packaging method such as flip-chip technology. Multiple individual chips are interconnected into a single, larger device by means of this packaging technique. Because each individual chip is extendible, the resulting larger capacity device has substantially the same architecture as the smaller devices from which it is made. This means that the final device is essentially equivalent to a higher capacity single device based on the architecture of the smaller component devices. In a preferred embodiment of the invention, the result is a high capacity programmable gate array having a semiconductor cost which increases substantially linearly with the number of gates, and which uses a straightforward extension of the development tools used for application designs based on the individual chips.

Claims9

Dependent claims

An extendible semiconductor based system, comprising:

a substrate having substrate bonding pads for the mounting of lower capacity logic arrays, the substrate bonding pads serving to electrically connect the lower capacity logic arrays to the substrate and to each other through interconnections on or within the substrate;
a plurality of lower capacity logic arrays mounted on the substrate to combine them into a higher capacity logic array, wherein each of the lower capacity logic arrays has an extendible architecture which includes a logic array bonding pad corresponding to each line which serves to propagate a signal entering or exiting an edge of the array, the logic array bonding pads on the edge of the array being connected to a corresponding substrate bonding pad, thereby serving to interconnect each line which propagates a signal entering or exiting the edge of a first array to a corresponding line of a second array;
and
a plurality of input/output bonding pads which electrically connect the lower capacity logic arrays to external pins on a mounting package, whereby a high capacity logic array having a higher capacity and the same functionality and architecture as the lower capacity logic arrays, and a semiconductor cost which increases substantially linearly with increasing capacity is produced.

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Dependencies are inferred from the claim text.