Method and apparatus for improvement of interconnection capacitance
AssigneeNational Semiconductor Corporation
InventorAli A. Iranmanesh
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Abstract
A method and apparatus for reducing interconnection capacitance. A lightly doped buried layer is provided in or on a substrate below a field oxide region. The capacitance of an interconnect on the field oxide is significantly reduced by the lightly doped buried layer. When using a p-type substrate, the lightly doped buried layer may, for example, be a lightly doped (10.sup.13 /cm.sup.3) n-type region. Junction capacitance of, for example, a bipolar transistor is also reduced.
Claims7
A process for forming semiconductor devices on a semiconductor wafer, said wafer comprising a dopant of a first conductivity type, comprising the steps of:
- a) forming a lightly doped region across substantially all of a surface of said wafer, wherein said lightly doped region is doped to a concentration of less than about 10.sup.14 /cm.sup.3 and said lightly doped region having a dopant concentration substantially less than said wafer;
- b) forming a plurality of devices on said wafer, at least a portion of said devices bounded by a field oxide region, said devices underlaid by said lightly doped region;
- and
- c) forming an interconnect region for at least some of said devices on at least a portion of said field oxide region.
A process for forming semiconductor devices on a semiconductor wafer, said wafer comprising a dopant of a first conductivity type, comprising the steps of:
- a) forming a lightly doped region across substantially all of a surface of said wafer, wherein said lightly doped region is doped to a concentration of between about 10.sup.12 and 10.sup.14 /cm.sup.3 and said lightly doped region having a dopant concentration substantially less than said wafer;
- b) forming a plurality of devices on said wafer, at least a portion of said devices bounded by a field oxide region, said devices underlaid by said lightly doped region;
- and
- c) forming an interconnect region for at least some of said devices on at least a portion of said field oxide region.
A process for forming semiconductor devices on a semiconductor wafer, said wafer comprising a dopant of a first conductivity type, comprising the steps of:
- a) forming a lightly doped region across substantially all of a surface of said wafer, wherein said lightly doped region is doped to a concentration of about 10.sup.13 /cm.sup.3 and said lightly doped region having a dopant concentration substantially less than said wafer;
- b) forming a plurality of devices on said wafer, at least a portion of said devices bounded by a field oxide region, said devices underlaid by said lightly doped region;
- and
- c) forming an interconnect region for at least some of said devices on at least a portion of said field oxide region.
A process for forming semiconductor devices on a semiconductor wafer, said wafer comprising a dopant of a first conductivity type, comprising the steps of:
- a) forming a lightly doped region across substantially all of a surface of said wafer, said lightly doped region having a dopant concentration substantially less than said wafer, wherein said lightly doped region is doped to a concentration of less than about 10.sup.14 /cm.sup.3 ;
- b) forming a first device and a second device on said wafer, at least a portion of said first device and said second device bounded by a field oxide region, said field oxide region formed in contact with said lightly doped region, said first device and said second device underlaid by said lightly doped region;
- and
- c) forming an interconnection on said field oxide and overlaying said lightly doped region to interconnect said first device and said second device.
A process for forming semiconductor devices on a semiconductor wafer, said wafer comprising a dopant of a first conductivity type, comprising the steps of:
- a) forming a lightly doped region across substantially all of a surface of said wafer, said lightly doped region having a dopant concentration substantially less than said wafer, wherein said lightly doped region is doped to a concentration of between about 10.sup.12 and 10.sup.14 /cm.sup.3 ;
- b) forming a first device and a second device on said wafer, at least a portion of said first device and said second device bounded by a field oxide region, said field oxide region formed in contact with said lightly doped region, said first device and said second device underlaid by said lightly doped region;
- and
- c) forming an interconnection on said field oxide and overlaying said lightly doped region to interconnect said first device and said second device.
A process for forming semiconductor devices on a semiconductor wafer, said wafer comprising a dopant of a first conductivity type, comprising the steps of:
- a) forming a lightly doped region across substantially all of a surface of said wafer, said lightly doped region having a dopant concentration substantially less than said wafer, wherein said lightly doped region is doped to a concentration of about 10.sup.13 /cm.sup.3 ;
- b) forming a first device and a second device on said wafer, at least a portion of said first device and said second device bounded by a field oxide region, said field oxide region formed in contact with said lightly doped region, said first device and said second device underlaid by said lightly doped region;
- and
- c) forming an interconnection on said field oxide and overlaying said lightly doped region to interconnect said first device and said second device.
Dependencies are inferred from the claim text.