Method of making dense vertical programmable read only memory cell structure
AssigneeSanDisk Corporation
InventorsJack H. Yuan, Gheorghe Samachisa, Daniel C. Guterman, Eliyahou Harari
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AssigneeSanDisk Corporation
InventorsJack H. Yuan, Gheorghe Samachisa, Daniel C. Guterman, Eliyahou Harari
Estimating the term…
A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.
In a process of forming an electrically programmable and erasable non-volatile memory device on a semiconductor substrate, a method of forming floating and erase gate structures, comprising the steps of:
A method of forming a memory device on a semiconductor substrate, comprising the steps of:
Dependencies are inferred from the claim text.