Method of manufacture of a split gate flash EEPROM memory cell

A method of fabricating an EEPROM device on a lightly doped semiconductor substrate comprising,

• forming a tunnel oxide dielectric layer on said substrate,
• forming a polysilicon I floating gate layer over said tunnel oxide dielectric layer,
• forming a PSG sacrificial layer on said floating gate layer,
• forming a split-gate channel mask over said sacrificial layer,
• etching said sacrificial layer and etching said floating gate layer using said split-gate channel mask to form a self-aligned channel mask for source/drain regions of said device,
• isotropically overetching said floating gate layer to form a floating gate therefrom,
• ion implanting to form a doped source region and a doped drain region in said substrate in a self-aligned process to define the channel of said device,
• removing said split-gate channel mask,
• removing the remainder of said sacrificial layer,
• forming a drain side mask over said floating gate and said source region,
• ion implanting to form a drain side N- region in said substrate,
• forming a blanket ONO interpolysilicon dielectric layer over said floating gate and said first dielectric layer,
• forming a blanket deposit of a polysilicon 2 control gate layer over said interpolysilicon layer,
• forming a control gate mask on said device,
• patterning said control gate layer by etching away material from said control gate layer through said openings in said control gate mask, and
• removing said control gate mask.

A method of fabricating an EEPROM device on a lightly doped semiconductor substrate comprising the steps in the sequence as follows:

• forming a tunnel oxide dielectric layer on said substrate,
• forming a polysilicon 1 floating gate layer over said tunnel oxide dielectric layer, said floating gate layer comprising a polysilicon layer having a thickness within a range between about 500.ANG. and about 2,000.ANG.,
• forming a PSG sacrificial layer on said floating gate layer, said PSG sacrificial layer having a thickness within a range between about 200.ANG. and about 1000.ANG.,
• forming a split-gate channel mask over said sacrificial layer,
• etching said sacrificial layer and said floating gate layer using said split gate channel mask to form a self-aligned channel mask for the source/drain regions of said device,
• isotropically overetching said floating gate layer to form a floating gate therefrom,
• ion implanting to forms doped source region and a doped drain region in said substrate in a self-aligned process to define the channel of said device, said source/drain implant formed by implantation of arsenic ions with a dose of about 5E15/cm.sup.2 at an energy of about 50 keV,
• removing said split-gate channel mask,
• removing the remainder of said sacrificial layer,
• forming a drain side mask over said floating gate and said source region,
• ion implanting to form a drain side N- region in said substrate, said drain side implant comprising implantation of phosphorus ions with a dose of about 1E14/cm.sup.2 at an energy of about 50 keV,
• forming a blanket ONO interpolysilicon dielectric layer over said floating gate and said first dielectric
• forming a blanket deposit of a polysilicon 2 control gate layer over said interpolysilicon layer, said control gate layer comprising a polysilicon layer having a thickness within a range between about 1,000.ANG. and about 5,000.ANG.,
• forming a control gate mask on said device,
• patterning said control gate layer by etching away material from said control gate layer through openings in said control gate mask, and
• removing said control gate mask.