Method for forming a planarization etch stop
AssigneeMotorola, Inc.
InventorTimothy J. Warfield
Life of this patent
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Abstract
A method for stopping a polish planarization wherein an etch-stop layer (13, 21, 31) is formed. The etch-stop layer (13, 21, 31) may be formed on a substrate (11) or on a conductive layer (12). The etch-stop layer (13, 21, 31) includes a metal and a grit material (17, 25, 35) such as a diamond powder. The etch-stop layer (13, 21, 31) serves as a stop to a mechanical polishing apparatus. The mechanical polishing apparatus removes a planarization layer (14, 22, 33) by polishing, but is unable to remove the etch-stop layer (13, 21, 31) because the etch-stop layer is able to withstand a polishing action of the mechanical polishing apparatus. The etch-stop layer (13, 21, 31) provides protection for the metal from mechanical damage during polish planarization and allows formation of a planar surface.
Claims18
A method for forming a planarization etch-stop, comprising the steps of:
- providing a monolithic integrated circuit having at least one conductive layer on the surface thereof;
- and
- forming a planarization etch-stop layer on a portion of the at least one conductive layer, the planarization etch-stop layer comprising a metal and a grit material, wherein the planarization etch-stop layer serves as an etch-sto for one of a chem-mechanical or mechanical etch.
A method for planarizing a monolithic semiconductor integrated circuit, comprising the steps of:
- providing the monolithic semiconductor integrated circuit;
- forming an etch-stop layer on a portion of the monolithic semiconductor integrated circuit, the etch-stop layer comprising a metal and a grit material;
- forming a planarization layer on the etch-stop layer;
- and
- planarizing the planarization layer using one of a chem-mechanical or a mechanical polish step.
A method for planarizing a monolithic semiconductor integrated circuit, comprising the steps of:
- providing the monolithic semiconductor integrated circuit;
- providing a first electroplating solution, the first electroplating solution comprising a metal;
- electroplating a first conductive layer on a portion of the monolithic semiconductor integrated circuit;
- providing a second electroplating solution, the second electroplating solution comprising the metal and a grit material;
- electroplating a second conductive layer on at least a portion of the first conductive layer, the second conductive layer comprising the metal and the grit material;
- forming a planarization layer on the second conductive layer;
- and
- planarizing the planarization layer, wherein the step of planarizing the planarization layer is stopped when the second conductive layer is encountered.
Dependencies are inferred from the claim text.