US 5,511,036 A · Flash EEPROM cell and array with bifurcated floating gates

Abstract

Each unit cell (10) of a flash EEPROM array (50) includes a source (18), a drain (20) and a channel (22) formed in a substrate (12). A thin tunnel oxide layer (32) is formed over the substrate (12) and P-Well (14). A bifurcated floating gate (34) is formed on the tunnel oxide layer (32) overlying the channel (22) , and includes a program arm (34a) which overlaps the drain (20), an erase arm (34b) which overlaps the source (18) and a base (34c) which extends around an end of the channel (22) and interconnects the program and erase arms (34a,34b). A thick gate oxide layer (36,36a) is formed over the floating gate (34), and a control gate (38) is formed over the gate oxide layer (36,36a). A central section of the control gate (38) which overlies a gap (34d) between the program and erase arms (34a, 34b) provides threshold voltage control for erasure. The erase arm (34b) spans the entire width of the channel (22), enabling erasure with low applied voltages. The bifurcated floating gate design automatically compensates for alignment error during fabrication such that the relative areas of the channel (22) which underlie the program/erase arms (34a, 34b) and gap (34d) are independent of the location of the gap (34d).

Claims19

Dependent claims

An electrically erasable programmable read-only memory (EEPROM) cell, comprising:

a semiconductor substrate;
a source and a drain formed in the substrate;
a channel which is formed in the substrate between the source and the drain and has a program region extending from the drain toward the source, an erase region extending from the source toward the drain and a gap region between said program and erase regions;
a tunnel insulating layer formed over the substrate;
a bifurcated floating gate which is formed over the tunnel insulating layer and includes:
a program arm overlying said program region of the channel;
an erase arm which overlies said erase region of the channel and overlaps the source;
and
a base which interconnects the program and erase arms;
a gate insulating layer formed over the program and erase arms of the floating gate and said gap region of the channel;
and
a control gate which is formed over the gate insulating layer and overlies said program and erase arms of the floating gate and said gap region of the channel.

9 more elements

An electrically erasable programmable read-only memory (EEPROM) array, comprising:

a semiconductor substrate;
an elongated drain region which is formed in the substrate and extends in a predetermined direction;
and
a plurality of first cells which are formed on the substrate extending from one side of said drain region and are spaced from each other in said predetermined direction;
and
a plurality of second cells which are formed on the substrate extending from an opposite side of said drain region and are spaced from each other in said predetermined direction;
each of said first and second cells including:
a drain which constitutes a portion of said drain region;
a source formed in the substrate;
a channel which is formed in the substrate between the source and the drain and has a program region extending from the drain toward the source, an erase region extending from the source toward the drain and a gap region between said program and erase regions;
a tunnel insulating layer formed over the substrate;
a bifurcated floating gate which is formed over the tunnel insulating layer and includes:
a program arm overlying said program region of the channel;
an erase arm which overlies said erase region of the channel and overlaps the source;
and
a base which interconnects the program and erase arms;
a gate insulating layer formed over the program and erase arms of the floating gate and said gap region of the channel;
and
a control gate which is formed over the gate insulating layer and overlies said program and erase arms of the floating gate and said gap region of the channel.

16 more elements

Dependencies are inferred from the claim text.

Flash EEPROM cell and array with bifurcated floating gates

Life of this patent

Flash EEPROM cell and array with bifurcated floating gates

Life of this patent

Abstract

Claims19