Multiple source equalization design for gate arrays and embedded arrays

A method for fabricating a plurality of integrated circuits from a plurality of alternate sources, each of said plurality of integrated circuits performing substantially identically regardless of inherent process differences of said plurality of alternate sources, comprising the steps of:

• designing a circuit to perform a desired electrical function;
• determining a first characteristic capacitance for a given electrical interconnect routing for an integrated circuit produced by a first alternate source using a first fabrication process;
• determining a second characteristic capacitance for a similar electrical interconnect routing for an integrated circuit produced by a second alternate source using a second fabrication process;
• determining a difference in said first and second characteristic capacitances;
• laying out said circuit to provide a first layout for fabrication by a first alternate source using said first fabrication process;
• and
• adjusting said first layout to adapt for said difference in said first and second characteristic capacitances to provide a second layout for fabrication by said second alternate source using said second fabrication process, wherein said step of adjusting said first layout to provide said second layout comprises the step of adjusting transistor channel widths to alter the speed of said transistors to compensate for said difference in characteristic capacitances.