Electrostatic discharge protective device having a reduced current leakage

An integrated structure for protecting integrated components connected to a pin of an integrated circuit which may be hit by an electrostatic discharge, the structure comprising:

• a pair of means for discharging connected in series between the pin and ground, with the discharging means opposing one another;
• and
• means for biasing connected between a node of interconnection between the discharging means and a supply voltage node to provide a voltage at the node greater than a maximum design voltage reached by the pin under normal conditions, said biasing means biasing said node of interconnection such that leakage current is limited during normal operation of the integrated circuit.

A protective network for protection of integrated components connected to pins of integrated circuits which may be hit by electrostatic discharges, the network comprising:

• a discharge zener diode connected between ground and an intermediate node of the network to which intermediate node a cathode of a protection diode of the network is connected, the anode of the protection diode being connected to a pin to be protected;
• and
• a biasing element connected between the intermediate node and a supply rail of the integrated circuit, to provide a voltage at the intermediate node greater than a maximum design voltage reached by the pin under normal operating conditions the biasing element including a forward biased junction, said biasing element biasing said intermediate node such that leakage current is limited during normal operation of the integrated circuit.

A protective network for protection of integrated components connected to pins of integrated circuits which may be hit by electrostatic discharges, the network comprising:

• means for discharging connected between ground and an intermediate node of the network to which intermediate node a cathode of a protection diode of the network is connected, the anode of the protection diode being connected to a pin to be protected;
• and
• means for biasing connected between the intermediate node and a supply rail of the integrated circuit, the biasing means including means for providing a voltage at the intermediate node greater than a maximum design voltage reached by the pin under normal conditions, said biasing means biasing said intermediate node such that leakage current is limited during normal operation of the integrated circuit.

An electrostatic protective device for protecting an input pin of an integrated circuit against an over voltage condition caused by an electrostatic discharge, the device including a pair of discharging elements connected in series between the pin and a voltage reference point, the pair of discharging elements including a parasitic transistor having a collector coupled to the pin, an emitter coupled to the voltage reference point, and a base coupled to an intermediate node of the pair of discharging elements, the improvement comprising a biasing element coupled between the intermediate node and a voltage supply rail, and wherein the biasing element provides a voltage at the intermediate node greater than a maximum design voltage reached by the pin under normal conditions to bias the parasitic transistor to an off state to limit leakage current through the pair of discharging elements.