Multi-finger input buffer with transistor gates capacitively coupled to ground
AssigneeVLSI Technology, Inc.
InventorTiao-Yuan Huang
Life of this patent
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Abstract
An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. Floating NMOS gates are capacitively coupled to V.sub.SS by a first-level metalization pattern. The metal-to-gate overlap capacitance and the gate-to-drain overlap capacitance define a voltage divider that leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer enter a conducting bipolar mode before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with gate array designs.
Claims3
A multi-finger input buffer for an integrated circuit comprising parallel buffer elements,
- each buffer element including:
- a pull-up device having a first node coupled to a logic high voltage and a second node coupled to an input voltage;
- and
- an NMOS pull-down transistor, the source of which is coupled to a logic low voltage, the drain of which is coupled to said input voltage, the gate of which is floating and capacitively coupled to a metal structure coupled to said logic low voltage;
- each said NMOS pull-down transistor having a respective first breakdown voltage and a respective second breakdown voltage so that said buffer elements are collectively characterized by a range of first breakdown voltages having a maximum first breakdown voltage, and by a range of second breakdown voltages having a minimum second breakdown voltage greater than said maximum first breakdown voltage.
Dependencies are inferred from the claim text.