Method of making vertical channel mask ROM

A method of manufacture of a semiconductor device on a P- silicon semiconductor substrate having a surface comprising

• a) forming an N+ source region layer on the surface of said semiconductor substrate, said N+ source layer having an exposed surface,
• b) forming a dielectric layer on the surface of said source region layer,
• c) patterning and etching said dielectric layer forming a first dielectric layer pattern with openings therein down to said exposed surface of said N+ source layer,
• d) forming a silicon epitaxial channel layer in said openings in said first dielectric layer pattern, said silicon epitaxial channel layer having exposed surfaces and doping said epitaxial layer with a P- dopant,
• e) forming an N+ drain layer on the surface of said silicon epitaxial layer to form drain regions over the remainder of said silicon epitaxial layer by doping with an N+ dopant,
• f) removing said dielectic layer and then forming a second dielectric layer on the surface of said device including said N+ drain layer,
• g) forming and patterning a conductor layer containing silicon over said second dielectric layer,
• h) forming an N+ implant mask with an N+ opening over a region of said epitaxial channel layer and ion implanting through said N+ opening in said implant mask into said region,
• i) forming a code implant mask over said conductor layer, and
• j) ion implanting through said code implant mask into the device.