Method of making a semiconductor device

A method of manufacturing a semiconductor device having a plurality of elements separated by element isolation films, each of said elements comprising:

• source and drain regions formed on a surface portion of a semiconductor substrate in spaced-apart relation from each other to define a channel region therebetween;
• a gate insulating film formed on said channel region;
• a floating gate disposed on said gate insulating film such that both ends thereof overlap end portions of said element isolation films bounding said surface portion;
• an insulating film formed to cover said floating gate;
• and a control gate disposed on said insulating film and on said element isolation films such that said control gate is formed in pan directly on said element isolation films and in part on said insulating film covering said floating gate whose ends in turn are formed directly on said element isolating films, said method comprising:
• a first process of forming an oxide layer on said substrate, forming an oxidization preventive film on said oxide layer and then forming openings in said oxidization preventative film;
• a second process of forming said element isolation films on portions of said semiconductor substrate exposed by said openings in said oxidization preventative film and then also forming channel stop diffusion layers in said semiconductor substrate along respective lower surfaces of said element isolation films by implanting ions in said semiconductor substrate, said element isolation films having a thickness at locations where said control gate is formed directly thereon and said channel stop diffusion layers having an impurity concentration such that first portions of the surface of said semiconductor substrate beneath said element isolation films at said locations where said control gate is formed directly on said element isolation films invert with respect to conducting type while second portions of the surface of the substrate beneath the element isolation films at locations where said control gate is not directly formed on said element isolation films do not invert, and wherein said first portions invert and said second portion do not invert with respect to conductivity type when said floating gate is subject to a potential at least equal to about 60% of a potential applied to the control gate;
• and
• a third process forming said element on each portion of said semiconductor substrate in spaced-apart relation from each other by means of said element isolation films and said channel stop diffusion layers.