Special interconnect layer employing offset trace layout for advanced multi-chip module packages

A method for multi-layer printed wiring board design comprising the steps of:

• establishing a first category of critical signals;
• defining design rules for first conductor spacing and first conductor characteristics to reduce degradation of the critical signals;
• identifying a favored direction for bus interconnection;
• defining a first orientation of adjacent signal planes to employ the first design rules having at least one "y" plane oriented at 0.degree. relative to the favored direction, at least one "x" plane separated from said y plane by a dielectric layer having conductors oriented at 90.degree. to the favored direction and at least one "y'" plane separated from said x plane by a dielectric layer having conductors oriented at 0.degree. with respect to the favored direction, said conductors of the "y'" plane offset from the conductors of the "y" plane by approximately one-half pitch;
• laying out at least one plurality of first signal planes using the first design rules and first orientation;
• establishing a second category of non-critical signals,
• defining second design rules for second conductor spacing and second conductor characteristics for said non-critical signals;
• and
• laying out at least one plurality of second signal planes employing the second design rules.