Random access memory device with trench-type one-transistor memory cell structure

A semiconductor memory device comprising:

• a semiconductor substrate;
• an array of memory cells subdivided into a plurality of cell sections on said substrate, each of said cell sections including a plurality of series connected memory cells connected to a corresponding bit line associated therewith, said series-connected memory cells each having trench capacitors and transfer-gate MOS transistors arrayed so that one of said capacitors and a corresponding one of said transistors constitute a memory cell;
• each of said trench capacitors including an insulated storage-node layer in a trench in said substrate, and an island-shaped layer at least partially covering said storage-node layer on said substrate to be coupled to said storage-node layer;
• each of said MOS transistors having a source and a drain defining therebetween a channel region in said substrate, and an insulated gate electrode at least partially overlying the channel region;
• and
• wherein each of said transfer-gate MOS transistors having one of its source and its drain having a first impurity-doped layer coupled to said island-shaped layer, wherein an adjacent transfer-gate MOS transistor of an adjacent memory cell in the same cell section having one of its source and its drain having a second impurity-doped layer coupled to said island-shaped layer, such that said island-shaped layer provides electrical continuity between said first impurity-doped layer of said transfer-gate MOS transistor and said second impurity-doped layer of said adjacent transfer-gate MOS transistor.

A series-connected memory cell array for use in a dynamic random access memory device, said array comprising:

• a substrate;
• a well region in said substrate;
• a plurality of memory cells on said substrate including transistors connected in series with one another, and trench-type capacitors each coupled to a corresponding one of said transistors to constitute a data storage cell, said transistors and said capacitors being positioned along a certain direction;
• said transistors each having a source and a drain defining a channel region in said well region, and an insulated gate overlying the channel region;
• said capacitors each having an impurity-doped semiconductor storage-node layer buried in a trench defined in said substrate to be greater in depth than said well region, causing said substrate to function as a common plate electrode;
• and
• a plurality of island-like layers arranged on said substrate to at least partially cover said storage-node layer at each of said capacitors in such a manner that adjacent ones of said transistors are electrically connected to each other by a corresponding one of said island-like layers.

A semiconductor memory device comprising:

• a semiconductor substrate;
• an array of one-transistor memory cells subdivided into a plurality of cell sections on said substrate, each of said cell sections including a preselected number of series-connected memory cells connected to a corresponding bit line associated therewith, said series-connected memory cells each having trench capacitors and transfer-gate MOS transistors alternately arrayed so that one of said capacitors and a corresponding one of said transistors constitute a memory cell;
• a semiconductor layer underlying the bit line on said substrate, said layer covering said trench capacitors;
• each of said trench capacitors including an insulated storage-node layer in a trench in said substrate;
• each of said MOS transistors having a source and a drain defining therebetween a channel region in said semiconductor layer, and an insulated gate overlying the channel region;
• and adjacent ones of said MOS transistors being coupled directly to each other at one of said source and said drain which is arranged on a corresponding one of said trench capacitors to be coupled to the storage-node layer therein;
• wherein said semiconductor layer comprises an elongate epitaxial semiconductor layer on said substrate;
• a dielectric layer sandwiched between said substrate and said semiconductor layer, said dielectric layer having an opening on each of said storage-node layers;
• and
• a field insulation film underlying said semiconductor layer.