Semiconductor integrated circuit device and process of manufacturing the same

A semiconductor integrated circuit device comprising a SRAM having a memory cell, the memory cell including a transfer MISFET to be controlled by a word line and a flip-flop circuit having a driver MISFET and a load MISFET, wherein said semiconductor integrated circuit device comprises:

• a first conductive film overlying a main surface of a semiconductor substrate and forming a gate electrode of said driver MISFET;
• a second conductive film overlying the main surface of said semiconductor substrate and forming a gate electrode of said transfer MISFET;
• a third conductive film overlying said first and second conductive films and forming a channel region, a source region and a drain region of said load MISFET;
• a fourth conductive film overlying said third conductive film and forming a gate electrode of said load MISFET;
• a dielectric film overlying said fourth conductive film and covering a memory cell array of said SRAM;
• a fifth conductive film overlying said dielectric film and covering said memory cell array, said fifth conductive film forming a plate electrode;
• a capacitance element constituted by said dielectric film, said gate electrode of said load MISFET and said plate electrode;
• and
• an opening in said plate electrode over the channel region at the drain region side of the load MISFET.

A semiconductor integrated circuit device comprising a SRAM having a memory cell, the memory cell including a transfer MISFET to be controlled by a word line and a flip-flop circuit having a driver MISFET and a load MISFET, wherein said semiconductor integrated circuit device comprises:

• a first conductive film overlying a main surface of a semiconductor substrate and forming a gate electrode of said driver MISFET;
• a second conductive film overlying the main surface of said semiconductor substrate and forming a gate electrode of said transfer MISFET;
• a third conductive film overlying said first and second conductive films and forming a plate electrode;
• a dielectric film overlying said third conductive film and covering said third conductive film;
• a fourth conductive film overlying said dielectric film and forming a gate electrode of said load MISFET;
• a fifth conductive film overlying said fourth conductive film and forming a channel region, a source region and a drain region of said load MISFET;
• a capacitance element constituted by said dielectric film, said gate electrode of said load MISFET and said plate electrode;
• and
• an opening in said plate electrode beneath the channel region at the drain region side of the load MISFET.

A semiconductor integrated circuit device comprising:

• a semiconductor substrate having a main surface;
• a plurality of static random access memory cells arranged in a row direction and in a column direction, each of said plurality of static random access memory cells including first and second driver MISFETs and first and second load MISFETs, each of said driver MISFETs having a gate electrode formed over said main surface and source and drain regions formed in said semiconductor substrate;
• a first insulating film formed over said driver MISFETs so as to cover said main surface;
• first conductive strips formed over said first insulating film, a source region, a drain region and a channel forming region of each of the first and second load MISFETs being formed in said first conductive strips, said drain regions of said first and second load MISFETs being electrically connected to said drain regions of said first and second driver MISFETs, respectively;
• gate electrodes of said first and second load MISFETs formed overlying said first insulating film such that a gate insulating film thereof intervenes between said gate electrodes and said first conductive strips, and such that, in a direction perpendicular to said main surface, said gate electrodes and said first conductive strips are laminated to overlap each other, said gate electrodes of said first and second load MISFETs being electrically connected to said drain regions of said second and first driver MISFETs, respectively;
• a second insulating film formed over said first conductive strips and said gate electrodes of said first and second load MISFETs;
• and
• a plate electrode layer formed over said second insulating film, such that one of a respective gate electrode and drain region, of said first and second load MISFETs, said second insulating film, and said plate electrode layer comprises a capacitance element,
• wherein respective gate electrodes and drain regions of said first and second load MISFETs are not overlapped to form an offset region in said channel forming region thereof in each of said memory cells, and wherein said plate electrode layer has openings such that the plate electrode layer does not cover said offset region.