Method of manufacturing a vertical field effect transistor
AssigneeNEC Corporation
InventorMasami Sawada
Life of this patent
Estimating the term…
Abstract
A vertical type field effect transistor includes N-type base regions formed on the surface of a P-type semiconductor substrate, a P-type source region formed in each of the N-type base regions, a gate insulating film formed between the P-type source regions, and a gate electrode formed of polysilicon on the gate insulating film. The transistor has the P-type source regions, the N-type base regions and a lower portion of the P-type semiconductor substrate as three terminals. A method for manufacturing the transistor comprises the steps of: forming the gate insulating film; growing a polysilicon layer; performing ion injection of an N-type impurity for the grown polysilicon layer; and performing heat treatment after the ion injection.
Claims8
A method for manufacturing a vertical type field effect transistor which includes N-type base regions formed on the surface of a P-type semiconductor substrate, a P-type source region formed in each of the N-type base regions, a gate insulating film formed between the P-type source regions, and a gate electrode formed of polysilicon on the gate insulating film, and has the P-type source regions, the N-type base regions and a lower portion of the P-type semiconductor substrate as three terminals, said method comprising the steps of:
- forming the gate insulating film;
- growing a polysilicon layer;
- performing a first ion implantation of an N-type impurity to the grown polysilicon layer;
- patterning said polysilicon layer into said gate electrode;
- forming the N-type base regions by ion implantation of an N-type impurity into said semiconductor substrate using said gate electrode as a mask;
- and
- performing heat treatment after the ion implantation.
A method for manufacturing a semiconductor device, comprising the steps of:
- forming a gate insulating film on a P-type semiconductor layer;
- forming a polysilicon layer on the gate insulating film;
- first doping an N-type impurity into said polysilicon layer;
- patterning said polysilicon layer into a gate electrode;
- second doping an N-type impurity into said gate electrode and said semiconductor layer;
- making the N-type impurity doped in said gate electrode diffuse toward the gate insulating film, the N-type impurity doped in the gate electrode not passing through the gate insulating film;
- and
- doping a P-type impurity into said gate electrode after the diffusion to make said gate electrode to be of a P-type.
A method for manufacturing a semiconductor device, comprising the steps of:
- forming a gate insulating film on a semiconductor substrate;
- growing a polysilicon layer on said gate insulating film;
- performing ion implantation of an N-type impurity with the dose amount of 1.times.10.sup.14 cm.sup.-2 or more to said polysilicon layer;
- patterning said polysilicon layer into a gate electrode after said ion implantation of an N-type impurity;
- forming an N-type base region by ion implantation of an N-type impurity into said semiconductor substrate using said gate electrode as a mask;
- performing heat treatment at a temperature of 1100.degree. C. or more, after said step of forming an N-type base region;
- performing ion implantation, after said heat treatment process, for doping P-type impurity into said gate electrode and said semiconductor substrate at a greater doping amount than said N-type impurity implanted into said polysilicon layer.
Dependencies are inferred from the claim text.