Current leakage reduction at the storage node diffusion region of a stacked-trench dram cell by selectively oxidizing the floor of the trench

Abstract

This invention constitutes a process for fabricating a structure which, when incorporated in an integrated circuit, will reduce current leakage into the substrate from transistor source/drain regions. The structure is particularly useful in dynamic random access memories, as it will minimize the effect of alpha particle radiation, thus improving the soft error rate. A trench is etched through the transistor source or drain region. A high dosage of oxygen ions is then implanted at low energy in the floor, but not the sidewalls of the trench. The resulting oxygen-implanted silicon layer at the bottom of the trench is then converted to a silicon dioxide barrier layer through rapid thermal processing or furnace annealing in an inert ambiance. The trench is then lined with a deposited contact layer that is rendered conductive either during or subsequent to deposition. Contact between the contact layer and the source or drain region is made through the sidewalls of the trench, which were not implanted with oxygen. The presence of the silicon dioxide barrier layer in a dynamic random access memory cell dramatically reduces the soft error rate by greatly reducing the area through which cell discharge can occur.

Dependencies are inferred from the claim text.