US 5,506,436 AGranted

Semiconductor memory cell

AssigneeSony Corporation

InventorsYutaka Hayashi, Takeshi Matsushita

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub. 2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.

Claims2

Dependent claims

A semiconductor memory cell comprising:

an information storage transistor comprising a first semiconductor channel layer having first and second opposing principal surfaces;
first and second conductive gates respectively disposed opposite said two principal surfaces of said first semiconductor channel layer with first and second barrier layers respectively interposed therebetween;
and first and second conductive regions each connected to either end of said first semiconductor channel layer, and
a switching transistor comprising a second semiconductor channel layer having third and fourth opposing principal surfaces;
third and fourth conductive gates respectively disposed opposite said two principal surfaces of said second semiconductor channel layer with third and fourth barrier layers respectively interposed therebetween;
and third and fourth conductive layers each connected to either end of said second semiconductor channel region, wherein
said fourth conductive layer is connected to said second conductive gate,
said first conductive gate and said third conductive gate are connected to a first memory-cell-selection line,
said first conductive layer and said third conductive layer are connected to a second memory-cell-selection line,
said second conductive layer is connected to a fixed potential including zero potential, and
said fourth conductive gate is connected to a read/write selection line.

8 more elements

Dependencies are inferred from the claim text.