Dynamic random access memory (DRAM) semiconductor device

A semiconductor device comprising:

• a semiconductor substrate of a first conductivity type;
• a trench type element isolation region formed in a preset depth from the semiconductor substrate surface;
• an element region of the first conductivity type surrounded by the element isolation region;
• a gate trench for forming a gate electrode, the gate trench being formed in the semiconductor substrate with a smaller depth than the element isolation region and extending through the element region and the element isolation region;
• a gate electrode buried in the bottom portion of the gate trench via a gate insulation film;
• source and drain regions of a second conductivity type formed in the element region and separated from each other by the gate trench;
• and
• a plate electrode which is disposed on the surface of the semiconductor substrate and on the side wall of the gate trench continuously so as to define one of a pair of capacitor electrodes;
• wherein the top surface of the gate electrode lies higher than the bottom levels of the source and drain regions and lower than a contact surface of the source and drain regions

A semiconductor device comprising:

• a semiconductor substrate of a first conductivity type;
• a trench type element isolation region formed in a preset depth from the semiconductor substrate surface;
• an element region of the first conductivity type surrounded by the element isolation region;
• a gate trench for forming a gate electrode, the gate trench being formed in the semiconductor substrate with a smaller depth than the element isolation region and extending through the element region and the element isolation region;
• a gate electrode buried in the bottom portion of the gate trench via a gate insulation film;
• source and drain regions of a second conductivity type formed in the element region and separated from each other by the gate trench;
• and
• a plate electrode which is buried in said gate trench and is opposite to one of said source and drain regions used as a storage node;
• wherein the top surface of the gate electrode lies higher than the bottom levels of the source and drain regions and lower than a contact surface of the source and drain regions.