Semiconductor device and a method of manufacturing thereof

A semiconductor device comprising:

• a semiconductor layer,
• an interlayer insulating layer formed on a surface of said semiconductor layer,
• a contact hole formed in said interlayer insulating layer to expose a contact portion of a surface of said semiconductor layer,
• a silicon plug layer embedded inside said contact hole, and having an upper surface which is essentially flat along its entire length,
• a first polycrystalline silicon layer formed on said interlayer insulating layer, and electrically connected to said silicon plug layer in said contact hole,
• a second polycrystalline silicon layer formed on a surface of said first polycrystalline silicon layer with an oxide film therebetween, and electrically connected to said first polycrystalline silicon layer by forming an opening in said oxide film in the proximity of a region right above said contact hole,
• wherein said first polycrystalline silicon layer and said second polycrystalline silicon layer have different types of conductivity,
• an intermediate conductive layer formed at least in a region between said first polycrystalline silicon layer and said second polycrystalline silicon layer for reducing a voltage drop in a pn junction.

A semiconductor device comprising:

• a semiconductor layer,
• an interlayer insulating layer formed on a surface of said semiconductor layer,
• a contact hole formed in said interlayer insulating layer to expose a contact portion of a surface of said semiconductor layer,
• a silicon plug layer embedded inside said contact hole, and having a plane surface,
• a first polycrystalline silicon layer formed on said interlayer insulating layer, and electrically connected to said silicon plug layer in said contact hole,
• a second polycrystalline silicon layer formed on a surface of said first polycrystalline silicon layer with an oxide film therebetween, and electrically connected to said first polycrystalline silicon layer by forming an opening in said oxide film in the proximity of a region right above said contact hole,
• wherein said first polycrystalline silicon layer and said second polycrystalline silicon layer have different types of conductivity,
• an intermediate conductive layer formed at least at a junction interface of in a region between said first polycrystalline silicon layer and said second polycrystalline silicon layer for reducing a voltage drop in a pn junction,
• wherein said intermediate conductive layer comprises a high concentration impurity layer formed to a predetermined depth from a surface of said first polycrystalline silicon layer in a region where said first polycrystalline silicon layer and said second polycrystalline silicon layer are connected, and
• wherein said silicon plug layer and said first polycrystalline silicon layer have different types of conductivity, and have an intermediate conductive layer further interposed at the junction interface to reduce a voltage drop at a pn junction.

A semiconductor device comprising:

• a semiconductor layer,
• an interlayer insulating layer formed on a surface of said semiconductor layer,
• a contact hole formed in said interlayer insulating layer to expose a contact portion of a surface of said semiconductor layer,
• a silicon plug layer embedded inside said contact hole, and having a plane surface,
• a first polycrystalline silicon layer formed on said interlayer insulating layer, and electrically connected to said silicon plug layer in said contact hole,
• a second polycrystalline silicon layer formed on a surface of said first polycrystalline silicon layer with an oxide film therebetween, and electrically connected to said first polycrystalline silicon layer by forming an opening in said oxide film in the proximity of a region right above said contact hole,
• wherein said first polycrystalline silicon layer and said second polycrystalline silicon layer have different types of conductivity,
• an intermediate conductive layer formed at least at a junction interface of in a region between said first polycrystalline silicon layer and said second polycrystalline silicon layer for reducing a voltage drop in a pn junction,
• wherein said intermediate conductive layer comprises a high concentration impurity layer formed to a predetermined depth from a surface of said first polycrystalline silicon layer in a region where said first polycrystalline silicon layer and said second polycrystalline silicon layer are connected, and
• wherein said silicon plug layer and said first polycrystalline silicon layer have different types of conductivity, and said high concentration impurity layer is formed in a region from an upper surface of said first polycrystalline silicon layer to the junction interface with said silicon plug layer.