CMOS structure with varying gate oxide thickness and with both different and like conductivity-type gate electrodes
AssigneeFuji Electric Co., Ltd.
InventorGen Tada
Life of this patent
Estimating the term…
Abstract
After forming a gate oxide film on the surface side of a single crystalline silicon substrate, a first polycrystalline silicon layer is subsequently formed. After that, portions of polycrystalline silicon layers are left in each gate electrode formation region of a high voltage drive circuit. Then, the gate oxide film in a low voltage drive circuit side is removed while maintaining this state. Then, after forming a gate oxide film on those surface sides, a polycrystalline silicon layer is subsequently formed in the surface side. After that, impurities are introduced into the polycrystalline silicon layer to provide it with electrical conduction, and then portions of polycrystalline silicon layers are left.
Claims4
A semiconductor device, comprising:
- a first MIS transistor circuit including a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor on a surface side of a semiconductor substrate, impurities of the same conductivity type being introduced into gate electrodes of said first MIS transistor and said second MIS transistor;
- and
- a second MIS transistor circuit including a first-conductivity-type third MIS transistor and a second-conductivity-type fourth MIS transistor, the thicknesses of gate insulating films of said third MIS transistor and said fourth MIS transistor being larger than the thicknesses of gate insulating films of said first MIS transistor and said second MIS transistor of said first MIS transistor circuit, a gate electrode of said first-conductivity-type third MIS transistor being formed of polycrystalline silicon into which a first-conductivity-type impurity is introduced, and a gate electrode of said second-conductivity-type fourth MIS transistor being formed of polycrystalline silicon into which a second-conductivity-type impurity is introduced.
A semiconductor device comprising:
- a low withstand voltage CMOS structure including an n-channel MOSFET having a polysilicon gate electrode doped with first-conductivity-type impurities, and a p-channel MOSFET having a polysilicon gate electrode doped with impurities of the same conductivity type as said first-conductivity-type impurities;
- and
- a high withstand voltage CMOS structure including an n-channel MOSFET having a polysilicon gate electrode doped with n-type impurities, and a p-channel MOSFET having a polysilicon gate electrode doped with p-type impurities.
Dependencies are inferred from the claim text.