US 5,497,014 A · BI-CMOS gate array semiconductor integrated circuits and internal cell structure involved in the same

Abstract

The invention provides a Bi-CMOS gate array semiconductor integrated circuit chip including a peripheral region including an input/output circuit region and a bonding pad region and an internal cell structure provided within an internal cell region involved in the semiconductor integrated circuit chip. The internal cell structure comprises MOS transistor cell units including a plurality of MOS transistors and bipolar transistor cell units including a plurality of bipolar transistors wherein a distribution ratio in the number of the MOS transistor cell units to the bipolar transistor cell units has such a variation that the distributed ratio is high in a region that requires driving of almost no or a small load while the distributed ratio is low in a region that requires driving of a large load.

Claims14

Dependent claims

An internal cell structure contained within an internal cell region of a semiconductor integrated circuit, comprising:

a plurality of MOS transistor cell units each including a plurality of MOS transistors;
and
a plurality of bipolar junction transistor cell units each including a plurality of bipolar junction transistors;
whereby a distribution ratio is obtained by comparing a number of said plurality of MOS transistor cell units to a number of said plurality of bipolar junction transistor cell units;
wherein said internal cell region comprises:
a first region having a high distribution ratio;
a third region having a low distribution ratio;
and
a second region having an intermediate distribution ratio which is lower in distribution ratio than said high distribution ratio and higher in distribution ratio than said low distribution ratio.

6 more elements

A Bi-CMOS gate array semiconductor integrated circuit chip, comprising:

a peripheral region comprising an input/output circuit region and a bonding pad region;
an internal cell structure contained with an internal cell region, comprising:
a plurality of MOS transistor cell units each including a plurality of MOS transistors;
and
a plurality of bipolar junction transistor cell units each including a plurality of bipolar junction transistors;
whereby a distribution ratio is obtained by comparing a number of said plurality of MOS transistor cell units to a number of said plurality of bipolar junction transistor cell units;
wherein said internal cell region comprises:
a first region having a high distribution ratio;
a third region having a low distribution ratio;
and
a second region having an intermediate distribution ratio which is lower in distribution ratio than said high distribution ratio and higher in distribution ratio than said low distribution ratio.

8 more elements

Dependencies are inferred from the claim text.

BI-CMOS gate array semiconductor integrated circuits and internal cell structure involved in the same

Life of this patent

BI-CMOS gate array semiconductor integrated circuits and internal cell structure involved in the same

Life of this patent

Abstract

Claims14