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US 5,497,011 AGranted
Semiconductor memory device and a method of using the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTomohide Terashima
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTomohide Terashima
Estimating the term…
In this semiconductor device, first, fifth and fourth impurity regions of a second conductivity type are formed on a main surface of a semiconductor layer of a first conductivity type with a predetermined space between each other. Second and third impurity regions of the first conductivity type are formed on the main surface of the first impurity region with a predetermined space between each other. A second gate electrode is formed between the second and third impurity regions. A first gate electrode is formed between the third impurity region and the semiconductor layer. A cathode electrode is connected to the third impurity region, and a short-circuit electrode is connected to first and second impurity regions. The first and fifth impurity regions are electrically short-circuited. Thereby, in the on state of the thyristor operation, the transistor including the second gate electrode can be off, whereby an entire hole current in the semiconductor layer forms a base current of one of the bipolar transistors, resulting in reduction of the holding current. Since the second gate electrode is provided independently from the first gate electrode, the gate length of the second gate electrode can be reduced, so that the on-resistance can be reduced, and thus the maximum controllable current can be increased.
A semiconductor device comprising:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Thyristors: lateral thyristors
Thyristors: with turn-on by field effect
With turn-off by field effect: produced by insulated gate structures
Inorganic electric semiconductor devices
Term ended 2 Jun 2015 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of using the same, and in particular to a semiconductor device used in a breakdown-resistive integrated circuit or a power integrated circuit as well as a method of using the same.
2. Description of the Background Art
FIG. 1 is a cross section showing a semiconductor device of a first embodiment of the invention;
FIG. 2 is an equivalent circuit diagram of the semiconductor device of the first embodiment shown in FIG. 1;
FIGS. 3 to 5 are cross sections showing first to third steps of the operation of the semiconductor device of the first embodiment shown in FIG. 1, respectively;
Embodiments of the invention will be described below with reference to the drawings.
Referring first to FIGS. 1 and 2, a semiconductor device of the first embodiment includes a semiconductor substrate 1 having a main surface on which an insulating film 3 is formed. An n.sup.- -SOI layer 2 is formed on insulating film 3. On the main surface of n.sup.- -SOI layer 2, there are formed p-diffusion regions 4, 5 and 6 with a predetermined space between each other. On the main surface of p-diffusion region 4, there are formed n.sup.+ -diffusion regions 7 and 8 with a predetermined space between each other. A second gate electrode 12 is formed on p-diffusion region 4 located between n.sup.+ -diffusion regions 7 and 8 with an insulating film 10 therebetween. A first gate electrode 11 is formed on the main surface of p-diffusion region 4 located between n.sup.+ -diffusion region 7 and n.sup.- -SOI layer 2 with an insulating film 9 therebetween.
The whole surface is covered with an insulating film 20. Contact holes are formed at predetermined regions of insulating film 20. A cathode electrode 13 is in contact with the main surface of n.sup.+ -diffusion region 7. An anode electrode 15 is in contact with the main surface of p-diffusion region 5. A short-circuit electrode 16 is in contact with the main surfaces of p-diffusion region 4 and n.sup.+ -diffusion region 8 as well as the main surface of p-diffusion region 6. An electrode 14 is formed at the rear surface of semiconductor substrate 1.