Semiconductor processing method of providing an electrically conductive interconnecting plug between an elevationally inner electrically conductive node and an elevationally outer electrically conductive node

A multi-metal layer semiconductor processing method comprising provision and patterning of at least two separate metal layers, the metal layers comprising an inner Metal 1 layer and an outer Metal 2 layer, the method comprising provision of an electrically conductive interconnecting plug between an elevationally inner conductive node location and the Metal 1 layer, the method comprising the following steps:

• providing an inner node location to which electrical connection is to be made;
• providing an electrically insulative layer outwardly over the inner node location;
• patterning and etching a contact opening through the insulative layer to the inner node location;
• providing a conductive plug within the contact opening to the inner node location, and providing an outermost fang gap between the conductive plug and the electrically insulative layer, the fang gap having a first width;
• widening the fang gap to a second width which is greater than the first width by a timed RF plasma etch of the electrically conductive material;
• providing a Metal 1 layer over the conductive plug after the widening step, the Metal 1 layer at least partially filling the widened fang gap;
• patterning the Metal 1 layer into a conductive line which electrically interconnects with the electrically conductive plug;
• and
• providing and patterning a Metal 2 layer outwardly of the Metal 1 layer.