Method for forming a nonvolatile memory device
AssigneeMotorola, Inc.
InventorsUmesh Sharma, Jim Hayden, Howard C. Kirsch
Life of this patent
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Abstract
A nonvolatile SRAM cell (20) includes a six-transistor SRAM cell portion (22) and a three-transistor nonvolatile memory portion (30). The nonvolatile memory portion (30) is connected to one storage node (101) of the SRAM cell portion (22). The nonvolatile SRAM cell (20) is three-dimensionally integrated in four layers of polysilicon. The nonvolatile memory portion (30) includes a thin film memory cell (32) having an oxide-nitride-oxide structure (41), and is programmable with a relatively low programming voltage. The three-dimensional integration of the nonvolatile SRAM cell (20) and relatively low programming voltage results in lower power consumption and smaller cell size.
Claims9
A method for forming an undergated thin film nonvolatile memory device comprising the steps of:
- providing an insulating substrate;
- forming a gate electrode overlying the insulating substrate;
- forming a sidewall spacer laterally adjacent to an edge of the gate electrode;
- depositing a first oxide layer overlying the insulating substrate and over a top surface of the gate electrode;
- depositing a silicon nitride layer over the first oxide layer;
- oxidizing a surface of the silicon nitride layer to form a relatively thin second oxide layer overlying the silicon nitride layer, wherein the second oxide layer is relatively thin compared to the first oxide layer;
- depositing a semiconductive layer overlying the second oxide layer;
- and
- implanting source and drain regions in the semiconductive layer.
A method for forming a thin film nonvolatile memory device comprising the steps of:
- providing an insulating substrate;
- depositing a semiconductive layer overlying the insulating substrate;
- depositing a gate oxide layer overlying the semiconductive layer;
- forming first and second gate electrodes overlying the gate oxide layer;
- etching a window region in the gate oxide layer between the first and second gate electrodes;
- forming a first oxide layer overlying the first and second gate electrodes and the window region;
- depositing a silicon nitride layer overlying the first oxide layer;
- depositing a second oxide layer overlying the silicon nitride layer, wherein the second oxide layer is relatively thick compared to the first oxide layer;
- forming a third gate electrode overlying the second oxide layer between the first and second gate electrodes, the third gate electrode overlying a portion of the first gate electrode and the second gate electrode;
- and
- implanting source and drain regions in the semiconductive layer.
Dependencies are inferred from the claim text.