US 5,496,751 A · Method of forming an ESD and hot carrier resistant integrated circuit structure

Abstract

An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate. A method of the present invention includes the steps of providing a semiconductor substrate, forming a gate over the substrate to define a channel, doping the substrate to form a pair of LDD regions in the substrate, doping the region to form a drain region and a source region, and doping the substrate to form a drain-side DDD region in the substrate which substantially separates the drain region from a drain-side LDD region and which substantially isolates the drain region from a bulk portion of the substrate, and to form a source-side DDD region in the substrate which substantially separates the source region from a source-side LDD region and substantially isolates the source region from a bulk portion of the substrate.

Claims16

Dependent claims

A method for making an integrated circuit device comprising:

providing a semiconductor substrate of a first polarity type and having a substantially planar substrate surface;
forming a gate over said substrate surface, thereby defining a channel in said substrate having a source side and a drain side;
forming a pair of LDD regions of a second polarity type in said substrate by ion implantation into said substrate at an angle between about 20.degree. C. and 60.degree. C. with respect to said substrate surface, where a drain side LDD region is adjacent to said drain side of said channel to provide hot carrier protection, and where a source side LDD region is adjacent to said source side of said channel;
forming dielectric spacers over said substrate surface on said drain side of said gate sidewall and on said source side of said gate sidewall after formation of said source and said drain side LDD regions;
forming a drain region in said substrate of said second polarity type at a higher doping level than that of said drain side LDD proximate said drain side LDD region and forming a source region of said second polarity type at a higher doping level than that of the source side LDD in said substrate proximate said source side LDD region by ion implantation into said substrate at an angle between about 80.degree. C. and 90.degree. C. with respect to said substrate surface after the formation of said spacers;
forming a drain side DDD region in said substrate after the formation of said dielectric spacers by ion implantation into said substrate at an angle between about 80.degree. C. and 90.degree. C. with respect to said substrate surface;
and
annealing the substrate to cause migration of the implanted ions such that said drain side DDD region and source side DDD region substantially enclose said respective drain and source regions, said DDD regions acting further to separate said drain and source regions from said respective drain and source side LDD regions.

5 more elements

A method for making an integrated circuit device having hot carrier and ESD protection comprising the steps of:

providing a semiconductor substrate of a first polarity type and having a substantially planar substrate surface;
forming a gate over said substrate surface, thereby defining a channel in said substrate having a source side and a drain side;
doping said substrate with a second polarity type by ion implantation into said substrate at an angle between 20.degree. C. and 60.degree. C. with respect to said substrate surface, to form a pair of LDD regions in the substrate, where a drain side LDD is adjacent to said drain side of said channel, and where a source side LDD region is adjacent to said source side of said channel;
forming dielectric spacers over said substrate on said drain side of said gate sidewall and on said source side of said gate sidewall after formation of said source and said drain side LDD regions and prior to formation of a source side DDD region and a drain side DDD region;
doping said substrate with said second polarity type after the formation of said dielectric spacers by ion implantation into said substrate at an angle between 80.degree. C. and 90.degree. C. with respect to said substrate surface, to form a drain region in said substrate proximate said drain side LDD region and to form a source region in said substrate proximate said source side LDD region;
and
doping said substrate with said second polarity type by ion implantation into said substrate at an angle between 80.degree. C. and 90.degree. C. with respect to said substrate surface and subsequently annealing the substrate to cause migration of the implanted ions to form said drain side DDD region in said substrate which separates said drain region from said drain side LDD region and isolates said drain region from a bulk portion of said substrate, and said source side DDD region in said substrate which separates said source region from said source side LDD region and isolates said source region from a bulk portion of said substrate to provide ESD protection.

4 more elements

Dependencies are inferred from the claim text.

Method of forming an ESD and hot carrier resistant integrated circuit structure

Life of this patent

Method of forming an ESD and hot carrier resistant integrated circuit structure

Life of this patent

Abstract

Claims16