US 5,495,394 AGranted

Three dimensional die packaging in multi-chip modules

AssigneeAT&T Global Information Solutions Company

InventorsBruce E. Kornfeld, Arthur R. Alexander

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Abstract

A multi-chip module wherein electrical components, such as integrated circuit devices, are packaged in a three dimensional arrangement. The multi-chip module includes a first, or upper, substrate including a signal layer formed on the top surface of the substrate and at least one integrated circuit device mounted to the top surface of the substrate and electrically connected to the signal layer. The module further includes a second, or internal, substrate, also including a first signal layer formed on the top surface of the substrate and at least one integrated circuit device mounted to the top surface of the substrate and electrically connected with the signal layer formed on the top surface of the second substrate. The second substrate includes a cavity through the substrate corresponding to each integrated circuit device mounted thereto. Each integrated circuit device mounted to the second substrate is placed within its corresponding cavity so that its top and bottom surfaces are flush with the top and bottom surfaces of the second substrate. Electrical signal paths are provided through the first substrate to electrically connect the integrated circuit devices mounted to the first and second substrates, and through the first and second substrates to electrically connect the multi-chip module components and circuitry to a printed circuit board to which the module is mounted. The multi-chip module may include two, three, or more signal layers and substrates connected as described herein.

A multi-chip module, comprising:

a first substrate including first and second surfaces, a signal layer formed on said first surface, and at least one integrated circuit device mounted to said first surface and electrically connected to said signal layer;
a second substrate including first and second surfaces;
a first signal layer formed on the first surface of said second substrate;
at least one cavity formed in said second substrate;
and an integrated circuit device corresponding to each of said cavities, mounted to the first surface of said second substrate and electrically connected with said first signal layer of said second substrate;
said first surface of said second substrate being attached to said second surface of said first substrate;
a plurality of electrical signal paths between the signal layers formed on the first surfaces of said first and second substrates for electrically connecting the integrated circuit devices mounted to said first and second substrates;
a second signal layer formed on the second surface of said second substrate;
at least one integrated circuit device mounted to said second surface of said second substrate and electrically connected with said second signal layer;
a plurality of electrical signal paths between said second signal layer and the signal layers formed on the first surfaces of said first and second substrates for electrically connecting the integrated circuit devices mounted to said second surface of said second substrate with the integrated circuit devices mounted to the first surfaces of said first and second substrates;
and
a third substrate having first and second surfaces and including a cavity corresponding to each integrated circuit device mounted to the second surface of said second substrate, the first surface of said third substrate being attached to the second surface of said second substrate such that said integrated circuit devices mounted to the second surface of said second substrate occupy the corresponding cavities in said third substrate;
and
wherein each integrated circuit device mounted to said second surface of said second substrate has a thickness equal to thickness of said third substrate, whereby the second surface of each integrated circuit device mounted to said second substrate is flush with the second surface of said third substrate to thereby provide thermal cooling of said integrated circuit devices mounted to said second surface of said second substrate.

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Abstract

Claims5