Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells

#This invention relates to integrated circuit manufacturing technology and, more specifically, to low-cost processes utilizing a reduced number of mask sets, for manufacturing CMOS dynamic random access memories. The instant process integrates stacked capacitor container-type cells in a "split-polysilicon" process flow in which N-channel and P-channel devices are patterned using separate masks.

#The business of producing dynamic random access memory (DRAM) devices is a very competitive, high-volume business. Process efficiency and manufacturability, as well as product quality, reliability, and performance are the key factors that determine the economic success of such a venture.

#Each cell within a DRAM device, an individually-addressable location for storing a single bit of digital data, is comprised of two main components: a field-effect access transistor and a capacitor. As component density in memory chips has increased, it has been necessary to at least maintain cell capacitance as cell size shrinks. Each new generation of DRAM devices generally has an integration level that is four times that of the generation which it replaced. Such a quadrupling of device number per chip is normally accompanied by a decrease in device geometries. All DRAM memories of 4-megabit and greater density utilize cell designs having three-dimensional capacitors. Although both trench and stacked capacitor designs have proven serviceable at the 4-megabit level, most manufacturers now seem to favor the stacked capacitor design for its manufacturability and somewhat higher yield.

#FIG. 1 is a cross-sectional view of a portion of an in-process dynamic random access memory at a stage of manufacture where N-well regions have been formed in a lightly-doped P-type substrate, silicon dioxide field isolation regions have been formed, a gate dielectric layer has been formed on active areas, and a three-layer sandwich, consisting of a first polysilicon layer which is doped to render it conductive, a silicon dioxide buffer layer and a thick silicon nitride layer, has been formed by sequential deposition steps;

#FIG. 2 is a cross-sectional view of the portion of the in-process memory of FIG. 1 following the patterning of the three-layer sandwich to form a series of wordlines in the N-channel region and an unetched expanse in the P-channel region (i.e., the N-well region);

#FIG. 3 is a cross-sectional view of the portion of the in-process memory of FIG. 2 following the blanket deposition of a silicon nitride spacer layer;

#Referring now to the cross-sectional view of the in-process DRAM circuitry FIG. 1, N-well regions 11 have been formed in a lightly-doped P-type substrate 12, silicon dioxide field isolation regions 13 have been formed, a gate dielectric layer 14 has been formed on active areas 15, and a three-layer stack 16, consisting of a first conductive layer 17, a silicon dioxide buffer layer 18 and a thick silicon nitride layer 19, has been formed by sequential deposition steps. Both N-channel and P-channel transistor gates will be formed from the three-layer stack 16. In a preferred embodiment of the process, the first conductive layer 17 is either doped polycrystalline silicon alone, or doped or undoped polycrystalline silicon that is coated with a refractory metal silicide to achieve reduced sheet resistance.

#Referring now to FIG. 2, the three-layer stack 16 of FIG. 1 has been patterned and etched to form a series of wordlines 21 in the N-channel region and an unetched three-layer expanse 22 in the P-channel region (i.e., the N-well region 11). The unetched three-layer expanse 22 is the distinguishing characteristic of a "split-polysilicon" CMOS DRAM process. At this point in the process, N-channel source/drain regions 23 are formed by implanting arsenic.

#Referring now to FIG. 3, a silicon nitride spacer layer 31 has been deposited over all in-process circuitry.