CMOS process and circuit including zero threshold transistors
AssigneeIMP, Inc.
InventorsMoiz Khambaty, Corey D. Petersen
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Abstract
A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FET' channels in addition to the implantation required to raise the PMOS FET' threshold voltage from the native threshold voltage to the normal threshold voltage.
Claims21
An integrated circuit comprising NMOS and PMOS FETs interconnected to form an operative electronic circuit, wherein some of said NMOS and PMOS FETs have a normal threshold voltage, said normal threshold voltage being in the range 0.6 to 1.1 volts for NMOS FETs and -0.6 to -1.1 volts for PMOS FETs, and wherein at least one of said PMOS FETs has a threshold voltage of -0.4 to 0.4 volts rather than the said normal threshold voltage.
An integrated circuit using a supply voltage of 3 volts or less comprising NMOS and PMOS FETs interconnected to form an operative electronic circuit, wherein some of said NMOS and PMOS FETs have a normal threshold voltage, said normal threshold voltage being in the range 0.6 to 1.1 volts for NMOS FETs and -0.6 to -1.1 volts for PMOS FETs, and wherein at least one of said PMOS FETs has a threshold voltage of -0.4 to 0.4 volts rather than the said normal threshold voltage.
An integrated circuit comprising NMOS and PMOS FETs interconnected to form an operative electronic circuit, wherein some of said NMOS and PMOS FETs have a normal threshold voltage, said normal threshold voltage being in the range 0.6 to 1.1 volts for NMOS FETs and -0.6 to -1.1 volts for PMOS FETs, and wherein at least one of said PMOS FETs has a threshold voltage of -0.4 to 0.4 volts rather than the said normal threshold voltage wherein the circuit includes analog circuitry.
Dependencies are inferred from the claim text.