US 5,493,142 A · Input/output transistors with optimized ESD protection

Abstract

An apparatus providing electrostatic discharge (ESD) protection in an input/output transistor. Disposed near the gate and the surface of the substrate is a lightly doped region. A sidewall oxide layer is selectively etched to extend laterally from a gate a significant amount. The sidewall oxide layer is also etched on an opposite side of the gate and may laterally extend an appreciable amount in that direction. A heavily doped source and drain are implanted in the substrate at areas of the surface exposed by etching, the drain separated from the gate by the significant extent of sidewall oxide. Near the surface of the substrate, the drain is separated from the gate by a similar extent of the lightly doped region, which provides a resistance in series between the drain and gate for ESD protection. The source may also be separated from the gate by a lightly doped region of appreciable extent, which acts as a series resistance between the source and the gate to mitigate ESD. The extent of the sidewall oxide, and thus the lightly doped regions separating the gate from the drain and source, can be tailored to optimize ESD protection and performance characteristics for a given application by defocusing snapback conduction.

Claims24

Dependent claims

An electrostatic discharge protection device for an integrated circuit chip comprising:

a semiconductor substrate with a terminal for communication external to the substrate disposed thereon,
a discharge structure disposed in said substrate having heavily doped regions of a first conductivity type forming a source and a drain with a channel of a second conductivity type disposed therebetween, said drain connected to said terminal and said source disposed distal to said terminal, said structure being characterized by a trigger voltage above which snapback conduction along a path between said source and said drain is initiated, a holding voltage above which said snapback conduction is sustained, and a maximum nondestructive current density along said path,
a lightly doped region of said first conductivity type forming a drain extension separating said drain and said channel and having a resistance in series with said path such that a flow of said maximum nondestructive current density along said path creates a voltage between said source and said drain along said path exceeding said trigger voltage, initiating snapback conduction in an adjacent path between said source and said drain.

An electrostatic discharge tolerant device for communication between an integrated circuit chip and a circuit external to the chip comprising:

a semiconductor chip with a surface having a bond pad disposed thereon,
a transistor having heavily doped subsurface source and drain regions separated by a channel region, with a gate disposed over said channel region and separated from said surface by a gate oxide layer, said drain region connected with said bond pad, a lightly doped drain extension disposed between said channel and said drain region,
a path between said source region and said drain region characterized by a trigger voltage initiating snapback conduction across said channel, a holding voltage sustaining said snapback conduction and a maximum nondestructive current density,
wherein said drain extension has a resistance in series with said path such that a flow of said maximum nondestructive current density along said path raises a voltage of said path above said trigger voltage, thereby initiating snapback conduction in an adjacent path.

1 more element

An input/output device for transmitting signals between an integrated circuit chip and a circuit external to the chip comprising:

a semiconductor substrate having a surface and a bond pad adjacent to said surface for communication between a circuit of said substrate and a circuit external to said substrate,
an active region of said substrate having doped sections near said surface forming a source and a drain of a first conductivity type separated by a channel of a second conductivity type, said drain connected to said bond pad,
a gate having a bottom disposed adjacent to said channel and separated from said surface by a gate oxide layer, said gate having a top distal to said surface,
a drain sidewall oxide layer disposed on said surface adjacent to said gate oxide layer and said drain and extending a distance along said surface away from said gate that is greater than a height of said top of said gate from said surface,
a lightly doped extension of said drain adjoining said drain sidewall oxide layer and said channel along said distance.

2 more elements

Dependencies are inferred from the claim text.

Input/output transistors with optimized ESD protection

Life of this patent

Input/output transistors with optimized ESD protection

Life of this patent

Abstract

Claims24