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US 5,493,133 AGranted
PNP punchthrough-assisted protection device for special applications in CMOS technologies
AssigneeTexas Instruments Incorporated
InventorsCharvaka Duvvury, Fernando D. Carvajal
Life of this patent
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Abstract
A protection circuit (40) providing positive and negative stress protection. A lateral PIN (58) assists in the triggering of a silicon-controlled rectifier (60) for positive stress protection. A vertical PNP (62) provides negative stress protection. A Schottky diode 64 may be used for biasing a n-well (44) to prevent latchup.
Claims12
A protection circuit for providing positive and negative stress protection, comprising:
- a. a lateral PNP connected between a bond pad and ground and comprising a first diffused region connected to said bond pad and a second diffused region connected to ground;
- b. a silicon-controlled rectifier connected between said bond pad and ground wherein said lateral PNP assists in the triggering of said silicon-controlled rectifier, said silicon-controlled rectifier comprising said first diffused region, a well region located in a substrate and a third diffused region located in said substrate;
- and
- c. a vertical PNP connected between said bond pad and ground and comprising said first diffused region, said-well region and said substrate connected to ground.
1 more element
A protection circuit for providing positive and negative stress protection, comprising:
- a. a substrate connected to ground;
- b. a well region formed in said substrate;
- c. a first p+ diffused region in said well region connected to a bond pad;
- d. a second p+ diffused region in said well region connected to ground;
- and
- e. a n+ diffused region in said substrate and connected to ground.
3 more elements
Dependencies are inferred from the claim text.