Capped reflow process to avoid contact autodoping and supress tungsten silicide peeling

A method of forming integrated circuits, comprising the steps of:

• providing a semiconductor substrate with devices formed therein;
• providing a gate dielectric layer formed on said semiconductor substrate;
• providing a polysilicon gate electrode formed on said gate dielectric layer;
• forming a tungsten silicide layer on said polysilicon gate electrode;
• forming a doped insulating dielectric layer with contact openings formed therein over said semiconductor substrate;
• forming an oxide layer over said doped insulating dielectric layer with contact openings wherein said oxide layer is formed using chemical vapor deposition of helium diluted tetraethoxysilane vapor and O.sub.2 and wherein said helium diluted tetraethoxysilane vapor is about 1 part tetraethoxysilane to between about 2 and 3 parts helium;
• reflowing said doped insulating dielectric layer;
• etching away said oxide layer;
• and
• forming a patterned metal electrode onto said semiconductor substrate.