Method of forming a capacitor in a semiconductor device

A method of forming a capacitor in a semiconductor device, comprising the steps of:

• sequentially forming an insulating layer and a first polysilicon layer on a silicon substrate having an impurity region;
• etching a portion of said first polysilicon layer to expose a portion of said insulating layer;
• sequentially depositing a first dielectric layer and a second polysilicon layer on said first polysilicon layer including said insulating layer;
• etching a portion of said first dielectric layer, said second polysilicon layer, and said insulating layer to expose said impurity region, thereby forming a contact hole;
• depositing a third polysilicon layer on the entire surface of the resulting structure including said second polysilicon layer and said impurity region exposed via said contact hole after forming said contact hole;
• depositing a CVD oxide layer on said third polysilicon layer and patterning said CVD oxide layer to include a portion of said CVD oxide layer at the center of said third polysilicon layer;
• depositing a fourth polysilicon layer on the entire surface of the resulting structure after patterning said CVD oxide layer;
• forming a photoresist pattern on said fourth polysilicon layer to expose first, second and third portions of said fourth polysilicon layer;
• removing said third polysilicon layer, said fourth polysilicon layer, said CVD oxide layer and said first dielectric layer exposed by said photoresist pattern;
• removing said photoresist pattern and sequentially depositing a second dielectric layer and a fifth polysilicon layer on the entire surface of the resulting structure after removing said photoresist pattern;
• etching portions of said fifth polysilicon layer and second dielectric layer to expose said first polysilicon layer;
• and
• depositing a sixth polysilicon layer on the entire surface of the resulting structure after etching said fifth polysilicon layer and second dielectric layer.

A method of forming a capacitor in a semiconductor device, comprising the steps of:

• sequentially forming an insulating layer and a first polysilicon layer on a silicon substrate having an impurity region;
• etching a portion of said first polysilicon layer to expose a portion of said insulating layer;
• sequentially depositing a first dielectric layer and a second polysilicon layer on said first polysilicon layer including said insulating layer;
• etching a portion of said first dielectric layer, said second polysilicon layer, and said insulating layer to expose said impurity region via a contact hole;
• depositing a third polysilicon layer on the entire surface of the resulting structure including said impurity region exposed by said contact hole, after forming said contact hole;
• depositing a CVD oxide layer on said third polysilicon layer and patterning said CVD oxide layer to retain a portion of said CVD oxide layer at the center of said third polysilicon layer;
• depositing a fourth polysilicon layer on the entire surface of the resulting structure after patterning said CVD oxide layer, and etching said third and fourth polysilicon layers exposed by patterning said CVD oxide layer to expose said first dielectric layer, thereby forming a fourth polysilicon spacer on the side walls of said CVD oxide layer;
• removing said first dielectric layer exposed by etching said third and fourth polysilicon layers to expose said first polysilicon layer and thereafter removing said CVD oxide layer;
• sequentially depositing a second dielectric layer and a fifth polysilicon layer on the entire surface of the resulting structure after removing said CVD oxide layer, and etching portions of said fifth polysilicon layer and second dielectric layer to expose said first polysilicon layer;
• and
• depositing a sixth polysilicon layer on the entire surface of the resulting structure after said fifth polysilicon layer and second dielectric layer.