Method for manufacturing a capacitor structure of a semiconductor memory device

A method for manufacturing a capacitor structure of an integrated semiconductor memory device comprising the steps of:

• forming a first conductive layer on a semiconductor substrate;
• forming a first material layer and a second material layer sequentially on said first conductive layer;
• patterning said second material layer to thereby form a first pattern;
• forming a third material layer on the resultant structure whereon said first pattern is formed;
• etching said third material layer anisotropically to thereby form a spacer on the side of said first pattern, and etching said first material layer simultaneously;
• etching said first conductive layer using said spacer as an etch-mask;
• removing said first pattern and said first material layer;
• forming a second conductive layer on the resultant structure;
• etching said second conductive layer anisotropically;
• and
• removing said spacer to thereby form a storage electrode of a capacitor.

A method for manufacturing a capacitor structure of an integrated semiconductor memory device comprising the steps of:

• forming a sacrificial material layer on a semiconductor substrate;
• forming a first conductive layer on said sacrificial material layer;
• forming a resist layer and an oxide layer on said first conductive layer;
• patterning said resist layer and said oxide layer to form a first pattern;
• forming a first material layer on said first conductive layer;
• etching said first material layer anisotropically to thereby form a first spacer on sidewalls of said first pattern;
• removing said first pattern;
• then
• forming a second conductive layer on the resultant structure;
• etching said second conductive layer anisotropically to thereby form a first cylindrical electrode on the side of said first spacer;
• forming a second material layer on the resultant structure whereon said first cylindrical electrode is formed;
• etching said second material layer anisotropically to thereby form a second spacer on the side of said first cylindrical electrode;
• forming a third conductive layer on the resultant structure whereon said second spacer is formed;
• etching said third conductive layer and said first conductive layer anisotropically using said sacrificial material layer as an etch end-point to thereby form a second cylindrical electrode on the side of said second spacer;
• and
• removing said first and second spacers together with said sacrificial layer to thereby form a storage electrode of a capacitor.

A method for manufacturing a capacitor structure of an integrated semiconductor memory device comprising the steps of:

• forming a sacrificial material layer on a semiconductor substrate;
• forming a first conductive layer on said sacrificial material layer;
• forming a first material layer and a second material layer sequentially on said first conductive layer;
• patterning said second material layer to thereby form a first pattern;
• forming a third material layer on at least one of said first material layer and said conductive material layer;
• etching said third material layer anisotropically to thereby form a spacer on the side of said first pattern, and etching said first material layer simultaneously;
• etching said first conductive layer using said spacer as an etch-mask and using said sacrificial material layer as an etch end-point;
• removing said first pattern and said first material layer;
• then
• forming a second conductive layer on the resultant structure;
• etching said second conductive layer anisotropically using said sacrificial material layer as an etch end-point;
• and
• removing said spacer to thereby form a storage electrode of a capacitor.