Method of making silicided LDD with recess in semiconductor substrate
AssigneeUnited Microelectronics Corp.
InventorChen-Chung Hsu
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Abstract
A process for fabricating MOSFET devices with a recessed lightly doped drain, (LDD), has been developed. This process initially involves conventional techniques of forming a silicided polysilicon, (polycide), gate structure, isolated from the silicided source and drain regions by a spacer sidewall insulator. The novel aspect of this process consists of removing the spacer insulator and etching a trench in the region between the metal silicided source/drain and the polycide gate structure. An angled ion implant is then performed to form lightly doped drain regions in the trench region, also extending under the polycide gate. This results in a narrowing of the channel length, thus enhancing device performance.
Claims18
A method for fabricating a MOSFET device on a semiconductor substrate having device regions formed therein comprising:
- forming field oxide regions for isolation of a device region on the surface of said substrate;
- growing a gate oxide on said device region;
- depositing a polysilicon layer over said field oxide regions and over said gate oxide;
- patterning to form a polysilicon gate structure within said device region on said gate oxide;
- depositing a first dielectric layer;
- anisotropically etching said first dielectric layer to form spacer insulators on sides of said polysilicon gate structure;
- ion implanting a first conductivity imparting dopant into said device regions and into said polysilicon gate;
- annealing to form source and drain regions;
- depositing a metal film on all exposed areas, including said field oxide, said source and drain regions, said space insulators and said polysilicon gate structure;
- annealing to form metal silicide on said source and drain regions and on said polysilicon gate structure and unreacted metal in all other areas;
- removal of said unreacted metal;
- removal of said spacer insulators, exposing a non-silicided portion of said semiconductor substrate;
- anisotropically etching said non-silicided substrate;
- ion implanting a second conductivity imparting dopant;
- growing a thermal oxide;
- and
- depositing a second dielectric layer.
A method for fabricating a MOSFET device on a semiconductor substrate having device regions formed therein comprising:
- forming field oxide regions for isolation of a device region on the surface of said substrate;
- growing a gate oxide on said device region;
- depositing a polysilicon layer over said field oxide regions and over said gate oxide;
- patterning to form a polysilicon gate structure within said device region on said gate oxide;
- depositing a first dielectric layer;
- anisotropically etching said first dielectric layer to form spacer insulators on sides of said polysilicon gate structure;
- ion implanting a first conductivity imparting dopant into said device regions and into said polysilicon gate;
- annealing to form source and drain regions;
- depositing a metal film on all exposed areas, including said field oxide, said source and drain regions, said space insulators, and said polysilicon gate structure;
- annealing to form metal silicide on said source and drain regions and on said polysilicon gate structure and unreacted metal in all other areas;
- removal of said unreacted metal;
- removal of said space insulators, exposing a non-silicided portion of said semiconductor substrate;
- anisotropically etching said non-silicided substrate to create a trench between said metal silicided polysilicon gate structure and said metal silicided source and drain regions;
- ion implanting a second conductivity imparting dopant into bottom and sides of said trench, and under edges of said metal silicided polysilicon gate structure to form lightly doped drain regions;
- growing a thermal oxide on exposed regions of said trench and on sides of said metal silicided polysilicon gate structure;
- and
- depositing a second dielectric layer, filling said trench, and overlying said metal silicided source and drain regions, said metal silicided polysilicon gate structure and said field oxide regions.
Dependencies are inferred from the claim text.